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diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index f80b17eda6a422b465e7c56fdf4f1dff18e4d4c8..86acf073d76142734130854a5fbb76fce0188c8c 100644 (file)
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -46,7 +46,14 @@ a 4 operand variant which becomes more along the lines of an FPGA:
         idx = RT[i] << 2 | RA[i] << 1 | RB[i]
         RT[i] = (RC & (1<<idx)) != 0
 
-mode may be used to do inversion of ordering, similar to carryless mul
+mode (3 bit) may be used to do inversion of ordering, similar to carryless mul.
+
+also, another possible variant involving swizzle and vec4:
+
+    for i in range(8):
+        idx = RA.x[i] << 2 | RA.y[i] << 1 | RA.z[i]
+        RT[i] = (RA.w[i] & (1<<idx)) != 0
+
 
 another mode selection would be CRs not Ints.