Fix r6 code bugs.

diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
index 8550457566a71dd8f10bbf34f767b907289ae66d..b1f78388e4f6d8f8064daef4d6abdce3fa32dbb8 100644 (file)
--- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c
+++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
@@ -188,6 +188,7 @@ int r600_cs_write_reloc(struct radeon_cs *cs,
     cs->crelocs++;
 
     radeon_bo_ref(bo);
+
     return 0;
 }
 
@@ -245,6 +246,8 @@ static int r600_cs_end(struct radeon_cs *cs,
     {
         fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n",
                 cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw);
+        fprintf(stderr, "cs->section_ndw = %d, cs->cdw = %d, cs->section_cdw = %d \n",
+                cs->section_ndw, cs->cdw, cs->section_cdw);
         fprintf(stderr, "CS section end at (%s,%s,%d)\n",
                 file, func, line);
         return -EPIPE;
@@ -356,7 +359,7 @@ static int r600_cs_emit(struct radeon_cs *cs)
     /* drm_r300_cmd_header_t age; */
     uint32_t length_dw_reloc_chunk;
     uint64_t ull;
-    uint64_t * chunk_ptrs[2];
+    uint64_t chunk_ptrs[2];
     uint32_t reloc_chunk[128]; 
     int r;
     int retry = 0;
@@ -370,23 +373,23 @@ static int r600_cs_emit(struct radeon_cs *cs)
     if (r) {
         return 0;
     }
-
+      
     /* raw ib chunk */
     cs_chunk[0].chunk_id   = RADEON_CHUNK_ID_IB;
     cs_chunk[0].length_dw  = cs->cdw;
-    cs_chunk[0].chunk_data = (uint64_t)(cs->packets);
+    cs_chunk[0].chunk_data = (unsigned long)(cs->packets);
 
     /* reloc chaunk */
     cs_chunk[1].chunk_id   = RADEON_CHUNK_ID_RELOCS;
     cs_chunk[1].length_dw  = length_dw_reloc_chunk;
-    cs_chunk[1].chunk_data = (uint64_t)&(reloc_chunk[0]);
+    cs_chunk[1].chunk_data = (unsigned long)&(reloc_chunk[0]);
 
-    chunk_ptrs[0] = (uint64_t * )&(cs_chunk[0]);
-    chunk_ptrs[1] = (uint64_t * )&(cs_chunk[1]);
+    chunk_ptrs[0] = (uint64_t)(unsigned long)&(cs_chunk[0]);
+    chunk_ptrs[1] = (uint64_t)(unsigned long)&(cs_chunk[1]);
 
     cs_cmd.num_chunks = 2;
-    cs_cmd.cs_id      = 0;
-    cs_cmd.chunks     = (uint64_t)&(chunk_ptrs[0]);
+    /* cs_cmd.cs_id      = 0; */
+    cs_cmd.chunks     = (uint64_t)(unsigned long)chunk_ptrs;
 
     /* dump_cmdbuf(cs); */
 

diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h
index dbb723b2b56c9475c26f05ddaa2722fe748e64f8..9ad73d9d3a800edc5be2514e8f64dc5124b342f0 100644 (file)
--- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h
+++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h
@@ -167,38 +167,38 @@ static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword)
 #define R600_OUT_BATCH_REGS(reg, num)                                  \
 do {                                                           \
        if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \
-               OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num)));   \
-               OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2);   \
+               R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num)));      \
+               R600_OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2);      \
        } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \
-               OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num)));  \
-               OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2);  \
+               R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num)));     \
+               R600_OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2);     \
        } else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \
-               OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num)));    \
-               OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2);    \
+               R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num)));       \
+               R600_OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2);       \
        } else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \
-               OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num)));     \
-               OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2);     \
+               R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num)));        \
+               R600_OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2);        \
        } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \
-               OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num)));      \
-               OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2);      \
+               R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \
+               R600_OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \
        } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \
-               OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num)));    \
-               OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2);    \
+               R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num)));       \
+               R600_OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2);       \
        } else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \
-               OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num)));   \
-               OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2);   \
+               R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num)));      \
+               R600_OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2);      \
        } else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \
-               OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num)));   \
-               OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2);   \
+               R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num)));      \
+               R600_OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2);      \
        } else {                                                        \
-               OUT_BATCH(CP_PACKET0((reg), (num))); \
+               R600_OUT_BATCH(CP_PACKET0((reg), (num))); \
        }                                                               \
 } while (0)
 
 /** Single register write to command buffer; requires 3 dwords for most things. */
 #define R600_OUT_BATCH_REGVAL(reg, val)                \
        R600_OUT_BATCH_REGS((reg), 1);          \
-       OUT_BATCH((val))
+       R600_OUT_BATCH((val))
 
 /** Continuous register range write to command buffer; requires 1 dword,
  * expects count dwords afterwards for register contents. */

diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index 3c8ba003d4d22b9714f8b299f8d06861dbf58f52..e6c03ecfd51e0c2dbc7c2c7084bc8c95b3dcb392 100644 (file)
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -448,3 +448,15 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual,
        return GL_TRUE;
 }
 
+/* Clean our own things only, radeonDestroyContext will do every thing else. */
+void
+r600DestroyContext (__DRIcontextPrivate * driContextPriv)
+{
+    GET_CURRENT_CONTEXT (ctx);
+    context_t *context = R700_CONTEXT(ctx);
+
+    (context->chipobj.DestroyChipObj)(context->chipobj.pvChipObj);
+}
+
+
+

diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h
index 70108b74c4730e6273e86497b346fa1b1a071c72..ae80037602a7691ac226d52ec9962723447c3d85 100644 (file)
--- a/src/mesa/drivers/dri/r600/r600_context.h
+++ b/src/mesa/drivers/dri/r600/r600_context.h
@@ -159,7 +159,7 @@ typedef struct chip_object
     void      *pvChipObj;
 
     /* ------------  OUT ------------------- */
-    GLboolean (*DestroyChipObj)(void* pvChipObj);
+    GLboolean (*DestroyChipObj)(GLcontext * ctx);
 
     void      (*InitFuncs)(struct dd_function_table *functions);
 
@@ -171,7 +171,8 @@ typedef struct chip_object
     GLboolean (*EmitShader)( GLcontext * ctx, 
                              void ** shaderbo,
                                         GLvoid * data, 
-                             int sizeinDWORD);
+                             int sizeinDWORD,
+                             char * szShaderUsage);
     GLboolean (*DeleteShader)(GLcontext * ctx, 
                               void * shaderbo);
     void      (*FreeDmaRegion)( GLcontext * ctx, 

diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c
index fc8f987cabda803a04f509ed00fd8dffba51caac..dee4cd3435fab96984105c28466fd7e5983d6cd1 100644 (file)
--- a/src/mesa/drivers/dri/r600/r600_emit.c
+++ b/src/mesa/drivers/dri/r600/r600_emit.c
@@ -175,7 +175,8 @@ void r600EmitCacheFlush(r600ContextPtr rmesa)
 GLboolean r600EmitShader(GLcontext * ctx, 
                          void ** shaderbo,
                                     GLvoid * data, 
-                         int sizeinDWORD) 
+                         int sizeinDWORD,
+                         char * szShaderUsage) 
 {
     radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
 
@@ -183,12 +184,22 @@ GLboolean r600EmitShader(GLcontext * ctx,
     uint32_t *out;
 
 shader_again_alloc:    
+#ifdef RADEON_DEBUG_BO
        pbo = radeon_bo_open(radeonctx->radeonScreen->bom,
                                             0, 
                          sizeinDWORD * 4, 
                          256, 
+                         RADEON_GEM_DOMAIN_GTT,
+                                            0,
+                         szShaderUsage);
+#else
+    pbo = radeon_bo_open(radeonctx->radeonScreen->bom,
+                                            0, 
+                         sizeinDWORD * 4, 
+                         256, 
                          RADEON_GEM_DOMAIN_GTT,
                                             0);
+#endif /* RADEON_DEBUG_BO */
 
        if (!pbo) 
     {
@@ -211,6 +222,8 @@ shader_again_alloc:
 
     memcpy(out, data, sizeinDWORD * 4);
 
+    radeon_bo_unmap(pbo); 
+
     *shaderbo = (void*)pbo;
 
     return GL_TRUE;

diff --git a/src/mesa/drivers/dri/r600/r600_emit.h b/src/mesa/drivers/dri/r600/r600_emit.h
index 11765c868c34c75015aa37d653923e24beba8baa..a2d8312287e8c6a95ddd4ba8df1ca0be449084c2 100644 (file)
--- a/src/mesa/drivers/dri/r600/r600_emit.h
+++ b/src/mesa/drivers/dri/r600/r600_emit.h
@@ -44,7 +44,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 extern GLboolean r600EmitShader(GLcontext * ctx, 
                                 void ** shaderbo,
                                            GLvoid * data, 
-                                int sizeinDWORD); 
+                                int sizeinDWORD,
+                                char * szShaderUsage); 
 
 extern GLboolean r600DeleteShader(GLcontext * ctx, 
                                  void * shaderbo);

diff --git a/src/mesa/drivers/dri/r600/r600_swtcl.c b/src/mesa/drivers/dri/r600/r600_swtcl.c
index 4d134070d65499907e4b3d289d845244231ec293..a60e7c942c2e49b4d8a5b6ce747aa7722900cb0b 100644 (file)
--- a/src/mesa/drivers/dri/r600/r600_swtcl.c
+++ b/src/mesa/drivers/dri/r600/r600_swtcl.c
@@ -594,8 +594,8 @@ static void r600EmitVertexAOS(r600ContextPtr rmesa, GLuint vertex_size, struct r
 
        BEGIN_BATCH(7);
        OUT_BATCH_PACKET3(R600_PACKET3_3D_LOAD_VBPNTR, 2);
-       OUT_BATCH(1);
-       OUT_BATCH(vertex_size | (vertex_size << 8));
+       R600_OUT_BATCH(1);
+       R600_OUT_BATCH(vertex_size | (vertex_size << 8));
        OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
        END_BATCH();
 #endif /* to be enabled */
@@ -612,7 +612,7 @@ static void r600EmitVbufPrim(r600ContextPtr rmesa, GLuint primitive, GLuint vert
 
        BEGIN_BATCH(3);
        OUT_BATCH_PACKET3(R600_PACKET3_3D_DRAW_VBUF_2, 0);
-       OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type);
+       R600_OUT_BATCH(R600_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type);
        END_BATCH();
 #endif /* to be enabled */
 }

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index e534bb11b29217c1b34a79a23faade95867d185a..1f160364fae338b8fd78fc289c4ad9c5e85f1de7 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -41,16 +41,27 @@
 
 extern const struct tnl_pipeline_stage *r700_pipeline[];
 
-static GLboolean r700DestroyChipObj(void* pvChipObj)
+static GLboolean r700DestroyChipObj(GLcontext * ctx)
 {
+    context_t * context = R700_CONTEXT(ctx);
     R700_CHIP_CONTEXT *r700;
 
-    if(NULL == pvChipObj)
+    if(NULL == context->chipobj.pvChipObj)
     {
         return GL_TRUE;
     }
 
-    r700 = (R700_CHIP_CONTEXT *)pvChipObj;
+    r700 = (R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj);
+
+    if(0 != r700->pbo_vs_clear)
+    {
+        (context->chipobj.DeleteShader)(context, r700->pbo_vs_clear);    
+    }
+
+    if(0 != r700->pbo_fs_clear)
+    {
+        (context->chipobj.DeleteShader)(context, r700->pbo_fs_clear);
+    }
 
     FREE(r700->pStateList);
 
@@ -405,19 +416,19 @@ void r700SetupVTXConstans(GLcontext  * ctx,
 
     BEGIN_BATCH_NO_AUTOSTATE(9);
 
-    OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); 
-    OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); 
+    R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
 
-    R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD1_0, 
+    R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, 
                          paos->bo, 
-                         uSQ_VTX_CONSTANT_WORD1_0,                                                      
+                         uSQ_VTX_CONSTANT_WORD0_0,                                                      
                          RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);    
-       OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
-       OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
-       OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
-       OUT_BATCH(0);
-       OUT_BATCH(0);
-       OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
+       R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
+       R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
+       R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
+       R600_OUT_BATCH(0);
+       R600_OUT_BATCH(0);
+       R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
 
     END_BATCH();
     COMMIT_BATCH();
@@ -440,13 +451,13 @@ int r700SetupStreams(GLcontext * ctx)
        unsigned int i;
 
     BEGIN_BATCH_NO_AUTOSTATE(6);
-    OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
-       OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
-    OUT_BATCH(0);
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
+       R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
+    R600_OUT_BATCH(0);
 
-    OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
-    OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
-    OUT_BATCH(0);
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
+    R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
+    R600_OUT_BATCH(0);
     END_BATCH();
     COMMIT_BATCH();
 
@@ -476,8 +487,33 @@ int r700SetupStreams(GLcontext * ctx)
     return R600_FALLBACK_NONE;
 }
 
+inline GLboolean needRelocReg(context_t *context, unsigned int reg)
+{
+    switch (reg + ASIC_CONTEXT_BASE_INDEX) 
+    {
+        case mmCB_COLOR0_BASE:
+        case mmCB_COLOR1_BASE:
+        case mmCB_COLOR2_BASE:
+        case mmCB_COLOR3_BASE:
+        case mmCB_COLOR4_BASE:
+        case mmCB_COLOR5_BASE:
+        case mmCB_COLOR6_BASE:
+        case mmCB_COLOR7_BASE: 
+        case mmDB_DEPTH_BASE:
+        case mmSQ_PGM_START_VS:   
+        case mmSQ_PGM_START_FS:            
+        case mmSQ_PGM_START_ES:            
+        case mmSQ_PGM_START_GS:            
+        case mmSQ_PGM_START_PS:        
+            return GL_TRUE;
+            break;
+    }
+
+    return GL_FALSE;
+}
+
 inline GLboolean setRelocReg(context_t *context, unsigned int reg,
-                             void * pbo_vs, void * pbo_fs)
+                             GLboolean bUseStockShader)
 {
     BATCH_LOCALS(&context->radeon);
     R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
@@ -507,9 +543,10 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg,
                     return GL_FALSE;
                 }
 
-                offset_mod.shift     = RIGHT_SHIFT;
-                offset_mod.shiftbits = 8;
-                offset_mod.mask      = 0x00FFFFFF;
+                /* refer to radeonCreateScreen : screen->fbLocation = (temp & 0xffff) << 16; */
+                offset_mod.shift     = NO_SHIFT;
+                offset_mod.shiftbits = 0;
+                offset_mod.mask      = 0xFFFFFFFF;
 
                 R600_OUT_BATCH_RELOC(r700->CB_COLOR0_BASE.u32All, 
                                      rrb->bo, 
@@ -524,9 +561,9 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg,
                 struct radeon_renderbuffer *rrb;
                 rrb = radeon_get_depthbuffer(&context->radeon);
 
-                offset_mod.shift     = RIGHT_SHIFT;
-                offset_mod.shiftbits = 8;
-                offset_mod.mask      = 0x00FFFFFF;
+                offset_mod.shift     = NO_SHIFT;
+                offset_mod.shiftbits = 0;
+                offset_mod.mask      = 0xFFFFFFFF;
 
                 R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, 
                                      rrb->bo, 
@@ -538,18 +575,25 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg,
             break;
         case mmSQ_PGM_START_VS:   
             {                
-                if(NULL != pbo_vs)
+                if(GL_TRUE == bUseStockShader)
                 {
-                    pbo = (struct radeon_bo *)pbo_vs;
+                    if(NULL != r700->pbo_vs_clear)
+                    {
+                        pbo = (struct radeon_bo *)(r700->pbo_vs_clear);
+                    }
+                    else
+                    {
+                        return GL_FALSE;
+                    }
                 }
                 else
                 {
                     pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
                 }
 
-                offset_mod.shift     = RIGHT_SHIFT;
-                offset_mod.shiftbits = 8;
-                offset_mod.mask      = 0x00FFFFFF;           
+                offset_mod.shift     = NO_SHIFT;
+                offset_mod.shiftbits = 0;
+                offset_mod.mask      = 0xFFFFFFFF;           
 
                 R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_VS.u32All, 
                                      pbo, 
@@ -563,18 +607,25 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg,
         case mmSQ_PGM_START_GS:            
         case mmSQ_PGM_START_PS:        
             {
-                if(NULL != pbo_fs)
+                if(GL_TRUE == bUseStockShader)
                 {
-                    pbo = (struct radeon_bo *)pbo_fs;
+                    if(NULL != r700->pbo_fs_clear)
+                    {
+                        pbo = (struct radeon_bo *)(r700->pbo_fs_clear);
+                    }
+                    else
+                    {
+                        return GL_FALSE;
+                    }
                 }
                 else
                 {
                     pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
                 }
 
-                offset_mod.shift     = RIGHT_SHIFT;
-                offset_mod.shiftbits = 8;
-                offset_mod.mask      = 0x00FFFFFF;
+                offset_mod.shift     = NO_SHIFT;
+                offset_mod.shiftbits = 0;
+                offset_mod.mask      = 0xFFFFFFFF;
 
                 voffset = 0;
                 R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_PS.u32All, 
@@ -589,7 +640,7 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg,
     return GL_FALSE;
 }
 
-GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs)
+GLboolean r700SendContextStates(context_t *context, GLboolean bUseStockShader)
 {
     BATCH_LOCALS(&context->radeon);
 
@@ -606,18 +657,22 @@ GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs
 
         pInit = pState;
 
-        while(NULL != pState->pNext)
+        if(GL_FALSE == needRelocReg(context, pState->unOffset))
         {
-            if( (pState->pNext->unOffset - pState->unOffset) > 1 )
+            while(NULL != pState->pNext)
             {
-                break;
-            }
-            else
-            {
-                pState = pState->pNext;
-                toSend++;
-            }
-        };
+                if( ((pState->pNext->unOffset - pState->unOffset) > 1)
+                    || (GL_TRUE == needRelocReg(context, pState->pNext->unOffset)) )
+                {
+                    break;
+                }
+                else
+                {
+                    pState = pState->pNext;
+                    toSend++;
+                }
+            };
+        }
 
         pState = pState->pNext;
 
@@ -625,10 +680,10 @@ GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs
         R600_OUT_BATCH_REGSEQ(((pInit->unOffset + ASIC_CONTEXT_BASE_INDEX)<<2), toSend);
         for(ui=0; ui<toSend; ui++)
         {
-            if( GL_FALSE == setRelocReg(context, (pInit->unOffset+ui), pbo_vs, pbo_fs) )
+            if( GL_FALSE == setRelocReg(context, (pInit->unOffset+ui), bUseStockShader) )
             {
                 /* for not reloc reg. */
-                OUT_BATCH(*(pInit->puiValue));
+                R600_OUT_BATCH(*(pInit->puiValue));
             }
             pInit = pInit->pNext;
         };

diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h
index 30ca2cab844612a2226dca10cbddaaad9c1b4845..42a72b7019f1b132837c7564bb0c856a5f700de5 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chip.h
+++ b/src/mesa/drivers/dri/r600/r700_chip.h
@@ -447,6 +447,8 @@ typedef struct _R700_CHIP_CONTEXT
 
     R700_TEXTURE_STATES texture_states;
 
+    void *    pbo_vs_clear;
+    void *    pbo_fs_clear;
     GLboolean bEnablePerspective;
        
 } R700_CHIP_CONTEXT;
@@ -454,7 +456,7 @@ typedef struct _R700_CHIP_CONTEXT
 #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(context->chipobj.pvChipObj))
 
 extern GLboolean r700InitChipObject(context_t *context);
-extern GLboolean r700SendContextStates(context_t *context, void * pbo_vs, void * pbo_fs);
+extern GLboolean r700SendContextStates(context_t *context, GLboolean bUseStockShader);
 extern int       r700SetupStreams(GLcontext * ctx);
 extern void      r700SetupVTXConstans(GLcontext  * ctx, 
                                       unsigned int nStreamID,

diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c
index 743875dfe2ffd7911f7d9d367d1ea05b884427ab..9a7cc000a67954e1ed85ed5db3d5ef62adbc853a 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_clear.c
+++ b/src/mesa/drivers/dri/r600/r700_clear.c
@@ -140,17 +140,18 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask)
 
     /* Setup vb */
     BEGIN_BATCH_NO_AUTOSTATE(6);
-    OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
-       OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
-    OUT_BATCH(0);
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
+       R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
+    R600_OUT_BATCH(0);
 
-    OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
-    OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
-    OUT_BATCH(0);
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
+    R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
+    R600_OUT_BATCH(0);
     END_BATCH();
     COMMIT_BATCH();
 
     (context->chipobj.EmitVec)(ctx, &aos_vb, (GLvoid *)fVb, 4, 16, 6);
+
     r700SetupVTXConstans(ctx, VERT_ATTRIB_POS, &aos_vb, 4, 16, 6);
 
     /* Setup shaders, copied from dump */
@@ -159,25 +160,33 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask)
        SETbit(r700->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
     SETbit(r700->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
         /* vs */
-    (context->chipobj.EmitShader)(ctx, &pbo_vs, (GLvoid *)(&uVs[0]), 28);
+    if(0 == r700->pbo_vs_clear)
+    {
+        (context->chipobj.EmitShader)(ctx, &(r700->pbo_vs_clear), (GLvoid *)(&uVs[0]), 28, "Clr VS");
+    }
+
     r700->SQ_PGM_START_VS.u32All     = 0;
     r700->SQ_PGM_RESOURCES_VS.u32All = 0x00800004;
 
             /* vs const */ /* TODO : Set color here */
     BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
-    OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, 4));
-    OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); 
-    OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[0])));
-    OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[1])));
-    OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[2])));
-    OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[3])));
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, 4));
+    R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4); 
+    R600_OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[0])));
+    R600_OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[1])));
+    R600_OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[2])));
+    R600_OUT_BATCH(*((unsigned int*)&(ctx->Color.ClearColor[3])));
     END_BATCH();
     COMMIT_BATCH();
 
     r700->SPI_VS_OUT_CONFIG.u32All   = 0x00000000;
        r700->SPI_PS_IN_CONTROL_0.u32All = 0x20000001;
         /* ps */
-    (context->chipobj.EmitShader)(ctx, &pbo_fs, (GLvoid *)(&uFs[0]), 12); 
+    if(0 == r700->pbo_fs_clear)
+    {
+        (context->chipobj.EmitShader)(ctx, &(r700->pbo_fs_clear), (GLvoid *)(&uFs[0]), 12, "Clr PS"); 
+    }
+
     r700->SQ_PGM_START_PS.u32All     = 0;
     r700->SQ_PGM_RESOURCES_PS.u32All = 0x00800002;
     r700->SQ_PGM_EXPORTS_PS.u32All   = 0x00000002;        
@@ -191,7 +200,7 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask)
     r700->SQ_PGM_START_GS.u32All     = 0;
 
     /* Now, send the states */
-    r700SendContextStates(context, pbo_vs, pbo_fs);
+    r700SendContextStates(context, GL_TRUE);
 
     /* Draw */
     GLuint numEntires, j;
@@ -209,38 +218,33 @@ static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask)
 
     SETfield(VGT_INDEX_TYPE, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
 
-    OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
-    OUT_BATCH(VGT_INDEX_TYPE);
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
+    R600_OUT_BATCH(VGT_INDEX_TYPE);
 
     VGT_NUM_INDICES = numIndices;
 
     SETfield(VGT_PRIMITIVE_TYPE, DI_PT_TRILIST, VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
 
-    OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
-    OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX);
-    OUT_BATCH(VGT_PRIMITIVE_TYPE);
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
+    R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX);
+    R600_OUT_BATCH(VGT_PRIMITIVE_TYPE);
 
     SETfield(VGT_DRAW_INITIATOR, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
     SETfield(VGT_DRAW_INITIATOR, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
 
-    OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1)));
-    OUT_BATCH(VGT_NUM_INDICES);
-    OUT_BATCH(VGT_DRAW_INITIATOR);
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1)));
+    R600_OUT_BATCH(VGT_NUM_INDICES);
+    R600_OUT_BATCH(VGT_DRAW_INITIATOR);
 
     for (j=0; j<numIndices; j++)
     {
-        OUT_BATCH(j);
+        R600_OUT_BATCH(j);
     }
     END_BATCH();
     COMMIT_BATCH();
 
     (context->chipobj.FlushCmdBuffer)(context);
 
-    /* TODO : keep these in context, don't load and release every time. */
-    (context->chipobj.DeleteShader)(context, &pbo_vs);
-
-    (context->chipobj.DeleteShader)(context, &pbo_fs);
-
     (context->chipobj.FreeDmaRegion)(context, aos_vb.bo);
 
     /* Restore chip object. */

diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c
index d06af109e57af416efc0f80a6000a58c671afd95..3aacad99197b75cc9b907a87f98ab473fec6adba 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_fragprog.c
+++ b/src/mesa/drivers/dri/r600/r700_fragprog.c
@@ -281,7 +281,8 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
         (context->chipobj.EmitShader)(ctx, 
                        &(fp->shaderbo), 
                        (GLvoid *)(fp->r700Shader.pProgram),
-                       fp->r700Shader.uShaderBinaryDWORDSize);                                         
+                       fp->r700Shader.uShaderBinaryDWORDSize,
+                       "FS");                                          
 
         fp->loaded = GL_TRUE;
     }
@@ -344,19 +345,19 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
 
         BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData);
         
-        OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData));
+        R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData));
 
         /* assembler map const from very beginning. */
-        OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
+        R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
 
         unNumParamData = paramList->NumParameters;
 
         for(ui=0; ui<unNumParamData; ui++)
         {
-            OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0])));
-            OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1])));
-            OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2])));
-            OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3])));
+            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0])));
+            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1])));
+            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2])));
+            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3])));
         }
         END_BATCH();
         COMMIT_BATCH();

diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.c b/src/mesa/drivers/dri/r600/r700_ioctl.c
index 7493efab0feedd01423f82ae72e1bd8ffc6eba09..1ab3ee7de5c39a285250d78dfdc6f0d1a73de811 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_ioctl.c
+++ b/src/mesa/drivers/dri/r600/r700_ioctl.c
@@ -60,7 +60,7 @@ static void r700Flush(GLcontext *ctx)
        if (radeon->dma.flush)
                radeon->dma.flush( ctx );
 
-       r700SendContextStates(context, NULL, NULL);
+       r700SendContextStates(context, GL_FALSE);
    
        if (radeon->cmdbuf.cs->cdw)
                rcommonFlushCmdBuf(radeon, __FUNCTION__);

diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index f338cf823cafc781b575cc290b6411a1b6df110a..aee6a68565de7b8cbdf272cb5e1af967c1c8d41d 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -59,9 +59,9 @@ void r700WaitForIdle(context_t *context)
     BATCH_LOCALS(&context->radeon);
     BEGIN_BATCH_NO_AUTOSTATE(3);
 
-    OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
-    OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
-    OUT_BATCH(1 << 15);
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
+    R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
+    R600_OUT_BATCH(1 << 15);
 
     END_BATCH();
     COMMIT_BATCH();
@@ -72,12 +72,12 @@ void r700WaitForIdleClean(context_t *context)
     BATCH_LOCALS(&context->radeon);
     BEGIN_BATCH_NO_AUTOSTATE(5);
 
-    OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
-    OUT_BATCH(0x16);
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
+    R600_OUT_BATCH(0x16);
 
-    OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
-    OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
-    OUT_BATCH(1 << 17); 
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
+    R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
+    R600_OUT_BATCH(1 << 17); 
 
     END_BATCH();
     COMMIT_BATCH();
@@ -89,15 +89,15 @@ static void r700Start3D(context_t *context)
     if (context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV670)
     {
         BEGIN_BATCH_NO_AUTOSTATE(2);
-        OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 1));
-        OUT_BATCH(0);
+        R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 1));
+        R600_OUT_BATCH(0);
         END_BATCH();        
     }
 
     BEGIN_BATCH_NO_AUTOSTATE(3);
-    OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1));
-    OUT_BATCH(0x80000000);
-    OUT_BATCH(0x80000000);
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1));
+    R600_OUT_BATCH(0x80000000);
+    R600_OUT_BATCH(0x80000000);
     END_BATCH();
 
     COMMIT_BATCH();
@@ -183,11 +183,11 @@ GLboolean r700SyncSurf(context_t *context)
 
     BEGIN_BATCH_NO_AUTOSTATE(5);
     
-    OUT_BATCH(CP_PACKET3((IT_SURFACE_SYNC << 8), 3)));
-    OUT_BATCH(CP_COHER_CNTL);
-    OUT_BATCH(0xFFFFFFFF);
-    OUT_BATCH(0x00000000);
-    OUT_BATCH(10);
+    R600_OUT_BATCH(CP_PACKET3((IT_SURFACE_SYNC << 8), 3)));
+    R600_OUT_BATCH(CP_COHER_CNTL);
+    R600_OUT_BATCH(0xFFFFFFFF);
+    R600_OUT_BATCH(0x00000000);
+    R600_OUT_BATCH(10);
 
     END_BATCH();
     COMMIT_BATCH();
@@ -241,7 +241,7 @@ static GLboolean r700RunRender(GLcontext * ctx,
 {
     context_t *context = R700_CONTEXT(ctx);
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj);
-
+#if 1
     BATCH_LOCALS(&context->radeon);
 
     unsigned int i, j;
@@ -286,7 +286,7 @@ static GLboolean r700RunRender(GLcontext * ctx,
     r700->SQ_PGM_START_ES.u32All     = r700->SQ_PGM_START_PS.u32All;
     r700->SQ_PGM_START_GS.u32All     = r700->SQ_PGM_START_PS.u32All;
 
-    r700SendContextStates(context, NULL, NULL);
+    r700SendContextStates(context, GL_FALSE);
 
     /* richard test code */
     for (i = 0; i < vb->PrimitiveCount; i++) 
@@ -305,33 +305,32 @@ static GLboolean r700RunRender(GLcontext * ctx,
         
         numEntires = 2 /* VGT_INDEX_TYPE */
                      + 3 /* VGT_PRIMITIVE_TYPE */
-                     + numIndices + 3 /* DRAW_INDEX_IMMD */
-                     + 2; /* test stamp */
+                     + numIndices + 3; /* DRAW_INDEX_IMMD */                  
                      
         BEGIN_BATCH_NO_AUTOSTATE(numEntires);  
 
         VGT_INDEX_TYPE |= DI_INDEX_SIZE_32_BIT << INDEX_TYPE_shift;
 
-        OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
-        OUT_BATCH(VGT_INDEX_TYPE);
+        R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
+        R600_OUT_BATCH(VGT_INDEX_TYPE);
 
         VGT_NUM_INDICES = numIndices;
 
         VGT_PRIMITIVE_TYPE |= r700PrimitiveType(prim) << VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift;
-        OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
-        OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX);
-        OUT_BATCH(VGT_PRIMITIVE_TYPE);
+        R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
+        R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX);
+        R600_OUT_BATCH(VGT_PRIMITIVE_TYPE);
 
         VGT_DRAW_INITIATOR |= DI_SRC_SEL_IMMEDIATE << SOURCE_SELECT_shift;
         VGT_DRAW_INITIATOR |= DI_MAJOR_MODE_0 << MAJOR_MODE_shift;
 
-        OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1)));
-        OUT_BATCH(VGT_NUM_INDICES);
-        OUT_BATCH(VGT_DRAW_INITIATOR);
+        R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1)));
+        R600_OUT_BATCH(VGT_NUM_INDICES);
+        R600_OUT_BATCH(VGT_DRAW_INITIATOR);
 
         for (j=0; j<numIndices; j++)
         {
-            OUT_BATCH(j);
+            R600_OUT_BATCH(j);
         }
         END_BATCH();
         COMMIT_BATCH();
@@ -339,8 +338,8 @@ static GLboolean r700RunRender(GLcontext * ctx,
 
     /* Flush render op cached for last several quads. */
     BEGIN_BATCH_NO_AUTOSTATE(2);
-    OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
-    OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT);
+    R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
+    R600_OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT);
     END_BATCH();
     COMMIT_BATCH();
 
@@ -354,7 +353,7 @@ static GLboolean r700RunRender(GLcontext * ctx,
     R600_OUT_BATCH_REGVAL((0x2144 << 2), 0x56785678);
     END_BATCH();
     COMMIT_BATCH();
-
+#endif //0
     rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ );
 
     return GL_FALSE;

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index a31a89627cb06c3fcce7720fee382e4095fcebc6..117d0add8b8e497b6c187232b747bf3775ff6176 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -692,7 +692,7 @@ void r700SetRenderTarget(context_t *context)
     nPitchInPixel = rrb->pitch/rrb->cpp;
     SETfield(r700->CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
              PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
-    SETfield(r700->CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * rrb->base.Height)/64 )-1,
+    SETfield(r700->CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
              SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
     r700->CB_COLOR0_BASE.u32All = 0;
     SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
@@ -737,7 +737,7 @@ void r700SetRenderTarget(context_t *context)
 
     SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
              PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
-    SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * rrb->base.Height)/64 )-1,
+    SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
              SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
 
     if(4 == rrb->cpp) 
@@ -909,7 +909,7 @@ void r700InitState(GLcontext * ctx) //-------------------
     r700->CB_COLOR0_FRAG.u32All   = 0;
     r700->CB_COLOR0_MASK.u32All   = 0;
 
-    r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
+       r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
 }
 
 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------

diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c
index f0dfbe20f0759de421fa4c70d132a457c4980fe0..4d113e2e0badbad90ec6cf7c3b486ca03be3c8aa 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_vertprog.c
+++ b/src/mesa/drivers/dri/r600/r700_vertprog.c
@@ -360,7 +360,8 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
         (context->chipobj.EmitShader)(ctx, 
                        &(vp->shaderbo), 
                        (GLvoid *)(vp->r700Shader.pProgram),
-                       vp->r700Shader.uShaderBinaryDWORDSize); 
+                       vp->r700Shader.uShaderBinaryDWORDSize,\r
+                       "VS"); 
 
         vp->loaded = GL_TRUE;
     }
@@ -405,18 +406,18 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
 
         BEGIN_BATCH_NO_AUTOSTATE(unNumParamData + 2); 
         
-        OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData));
+        R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData));
         /* assembler map const from very beginning. */
-        OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
+        R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
 
         unNumParamData = paramList->NumParameters;
 
         for(ui=0; ui<unNumParamData; ui++)
         {
-            OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0])));
-            OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1])));
-            OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2])));
-            OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3])));
+            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][0])));
+            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][1])));
+            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][2])));
+            R600_OUT_BATCH(*((unsigned int*)&(paramList->ParameterValues[ui][3])));
         }
         END_BATCH();
         COMMIT_BATCH();

diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index f8a29fdba083d93b94db67b9e463dd9ab8ceb5cc..30c858fce0f497b943d1e7c0630c1727868c04d7 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -216,6 +216,11 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
        radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
        radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
 
+    /* +r6/r7 */
+    __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
+       radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
+    /* --------- */
+
        if (radeon == current) {
                radeon_firevertices(radeon);
                _mesa_make_current(NULL, NULL, NULL);
@@ -224,6 +229,13 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
        assert(radeon);
        if (radeon) {
 
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */
+           if (IS_R600_CLASS(screen))
+        {
+                   r600DestroyContext(driContextPriv);
+        }
+#endif
+
                if (radeon->dma.current) {
                        rcommonFlushCmdBuf( radeon, __FUNCTION__ );
                }

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index be3b816b865ed04417b6f367278cbe2e432718d8..1d26e2c40a04ecd9926d8972c14ab59e3ad21f29 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -1086,16 +1086,38 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
    screen->AGPMode = dri_priv->AGPMode;
 
    ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp);
-   if (ret) {
-       if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
-          screen->fbLocation      = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
-       else {
-           FREE( screen );
-           fprintf(stderr, "Unable to get fb location need newer drm\n");
-           return NULL;
+   
+   /* +r6/r7 */
+   if(screen->chip_family >= CHIP_FAMILY_R600)
+   {
+       if (ret) 
+       {
+            FREE( screen );
+            fprintf(stderr, "Unable to get fb location need newer drm\n");
+            return NULL;
        }
-   } else {
-       screen->fbLocation = (temp & 0xffff) << 16;
+       else
+       {
+            screen->fbLocation = (temp & 0xffff) << 24;
+       }
+   }
+   else
+   {
+        if (ret) 
+        {
+            if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
+                   screen->fbLocation      = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
+            else 
+            {
+                FREE( screen );
+                fprintf(stderr, "Unable to get fb location need newer drm\n");
+                return NULL;
+            }
+        } 
+        else 
+        {
+            screen->fbLocation = (temp & 0xffff) << 16;
+        }
    }
 
    if (IS_R300_CLASS(screen)) {