arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 banking

Change-Id: Ic08ac1e7f3ebef408a83aa068ce15e9dfe2aa3cd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20628
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 81bc3efae0f9b41e23019ea1b372d3eed527995d..bffb4446ab27d6258e35f63af0e48cb619b759b9 100644 (file)
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4646,7 +4646,7 @@ ISA::initializeMiscRegMetadata()
         .allPrivileges().exceptUserMode()
         .mapsTo(MISCREG_ICC_IGRPEN0);
     InitReg(MISCREG_ICC_IGRPEN1_EL1)
-        .banked()
+        .banked64()
         .mapsTo(MISCREG_ICC_IGRPEN1);
     InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
         .bankedChild()

diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index 0d444f16564fb0210591b0734d53fb376baa2e77..b793f7c283d0f9c29727c793addd2231e4521ddc 100644 (file)
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -191,6 +191,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
               return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
           }
 
+          value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1);
           break;
       }
 
@@ -1358,7 +1359,8 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
                                       icc_igrpen1_el3);
           }
 
-          break;
+          setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
+          return;
       }
 
       // Virtual Interrupt Group 1 Enable register