/*
- * Copyright (c) 2010-2013, 2016-2019 ARM Limited
+ * Copyright (c) 2010-2013, 2016-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
}
}
+void
+TLB::flushAll()
+{
+ DPRINTF(TLB, "Flushing all TLB entries\n");
+ int x = 0;
+ TlbEntry *te;
+ while (x < size) {
+ te = &table[x];
+
+ DPRINTF(TLB, " - %s\n", te->print());
+ te->valid = false;
+ stats.flushedEntries++;
+ ++x;
+ }
+
+ stats.flushTlb++;
+
+ // If there's a second stage TLB (and we're not it) then flush it as well
+ if (!isStage2) {
+ stage2Tlb->flushAll();
+ }
+}
+
void
TLB::flushAllSecurity(bool secure_lookup, ExceptionLevel target_el,
bool ignore_el, bool in_host)
/*
- * Copyright (c) 2010-2013, 2016, 2019 ARM Limited
+ * Copyright (c) 2010-2013, 2016, 2019-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
bool checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req,
Mode mode);
+ /** Reset the entire TLB. Used for CPU switching to prevent stale
+ * translations after multiple switches
+ */
+ void flushAll() override;
+
/** Reset the entire TLB
* @param secure_lookup if the operation affects the secure world
void flushAllNs(ExceptionLevel target_el, bool ignore_el = false);
- /** Reset the entire TLB. Used for CPU switching to prevent stale
- * translations after multiple switches
- */
- void flushAll() override
- {
- flushAllSecurity(false, EL0, true, false);
- flushAllSecurity(true, EL0, true, false);
- }
-
/** Remove any entries that match both a va and asn
* @param mva virtual address to flush
* @param asn contextid/asn to flush on match