Added ENABLE_NDEBUG makefile options

diff --git a/Makefile b/Makefile
index 18aa95cc1abd5819c0a7e0e6bf72bb54db0bf078..36d5edb398a4007ec0b970a18352c3364fe3f9dc 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -15,6 +15,7 @@ ENABLE_COVER := 1
 
 # other configuration flags
 ENABLE_GPROF := 0
+ENABLE_NDEBUG := 0
 
 DESTDIR := /usr/local
 INSTALL_SUDO :=
@@ -133,6 +134,10 @@ CXXFLAGS += -pg
 LDFLAGS += -pg
 endif
 
+ifeq ($(ENABLE_NDEBUG),1)
+CXXFLAGS := -O3 -DNDEBUG $(filter-out -Os,$(CXXFLAGS))
+endif
+
 ifeq ($(ENABLE_ABC),1)
 CXXFLAGS += -DYOSYS_ENABLE_ABC
 TARGETS += yosys-abc$(EXE)

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 5bd71716e6e0075f8ac4ba016c4f3e94d66d08c5..c8fbf8d6798c8314695568be861ab87bb5045780 100644 (file)
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -479,7 +479,7 @@ struct BtorDumper
                                log_assert(!(cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" ||
                                        cell->type == "$ge" || cell->type == "$gt") || output_width == 1);
                                bool l1_signed = cell->parameters.at(RTLIL::IdString("\\A_SIGNED")).as_bool();
-                               bool l2_signed = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
+                               bool l2_signed YS_ATTRIBUTE(unused) = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
                                int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
                                int l2_width =  cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
                                
@@ -820,7 +820,7 @@ struct BtorDumper
                                int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
                                log_assert(input->size() == input_width);
                                int input_line = dump_sigspec(input, input_width);
-                               const RTLIL::SigSpec* output = &cell->getPort(RTLIL::IdString("\\Y"));
+                               const RTLIL::SigSpec* output YS_ATTRIBUTE(unused) = &cell->getPort(RTLIL::IdString("\\Y"));
                                int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
                                log_assert(output->size() == output_width);
                                int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int(); 

diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index 6a6974133b21879ba06efca8494bdd713051d125..80e429e9147869f8c3c3dae3c54875855c937c26 100644 (file)
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -336,7 +336,9 @@ void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
 
 void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
 {
+#ifndef NDEBUG
        int init_autoidx = autoidx;
+#endif
 
        if (!flag_m) {
                int count_selected_mods = 0;

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 6128ac68471dbb9c18c8771660802c170cc7ead6..e9750eba64c0bd4210247e87275825b2dd521183 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -2309,8 +2309,10 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
        flags &= ~children_flags | backup_flags;
 
        if (proc_flags_p) {
+#ifndef NDEBUG
                for (auto it : *proc_flags_p)
                        log_assert((it.second & ~0xff000000) == 0);
+#endif
                delete proc_flags_p;
        }
 }

diff --git a/kernel/log.h b/kernel/log.h
index 8b3d8a3ad0c9b90e5f8a20614faccbe2ce1f1d94..fd35c7bf71ae02e37135bc6efbcb8f9361063c24 100644 (file)
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -220,7 +220,7 @@ static inline void log_dump_val_worker(char *v) { log("%s", v); }
 static inline void log_dump_val_worker(const char *v) { log("%s", v); }
 static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); }
 static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p.sec()); }
-static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }
+static inline void log_dump_args_worker(const char *p YS_ATTRIBUTE(unused)) { log_assert(*p == 0); }
 void log_dump_val_worker(RTLIL::SigSpec v);
 
 template<typename T>

diff --git a/kernel/macc.h b/kernel/macc.h
index ab17f8c41de7c4ce4e83b49590e4186ca222bdb6..cac5b00d7c3cb278f08fd8f54fd6c2976ba8a04d 100644 (file)
--- a/kernel/macc.h
+++ b/kernel/macc.h
@@ -105,10 +105,12 @@ struct Macc
                bit_ports = cell->getPort("\\B");
 
                std::vector<RTLIL::State> config_bits = cell->getParam("\\CONFIG").bits;
-               int config_width = cell->getParam("\\CONFIG_WIDTH").as_int();
                int config_cursor = 0;
 
+#ifndef NDEBUG
+               int config_width = cell->getParam("\\CONFIG_WIDTH").as_int();
                log_assert(GetSize(config_bits) >= config_width);
+#endif
 
                int num_bits = 0;
                if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 1;

diff --git a/kernel/modtools.h b/kernel/modtools.h
index 113b0918d591b42c8aa7a394b44fd882e6e82e3c..5fd7ef5a6ed05f2dd7fa76bbf1f2e55b827c7bef 100644 (file)
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -130,7 +130,7 @@ struct ModIndex : public RTLIL::Monitor
                port_add(cell, port, sig);
        }
 
-       virtual void notify_connect(RTLIL::Module *mod, const RTLIL::SigSig &sigsig) YS_OVERRIDE
+       virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE
        {
                log_assert(module == mod);
 
@@ -174,13 +174,13 @@ struct ModIndex : public RTLIL::Monitor
                }
        }
 
-       virtual void notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&) YS_OVERRIDE
+       virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) YS_OVERRIDE
        {
                log_assert(module == mod);
                auto_reload_module = true;
        }
 
-       virtual void notify_blackout(RTLIL::Module *mod) YS_OVERRIDE
+       virtual void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE
        {
                log_assert(module == mod);
                auto_reload_module = true;

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index ac1bc7abfaa5b5767cc3fa7a869f913532ef84e3..d5467afe1b423e67cb8f3620b3a7b8cc23b7cb98 100644 (file)
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -319,11 +319,13 @@ std::string make_temp_dir(std::string template_str)
        mkdir(template_str.c_str());
        return template_str;
 #else
+#  ifndef NDEBUG
        size_t pos = template_str.rfind("XXXXXX");
        log_assert(pos != std::string::npos);
 
        int suffixlen = GetSize(template_str) - pos - 6;
        log_assert(suffixlen == 0);
+#  endif
 
        char *p = strdup(template_str.c_str());
        p = mkdtemp(p);

diff --git a/libs/ezsat/ezsat.cc b/libs/ezsat/ezsat.cc
index 1224fd3a9a9a31f8c1007a12e78b461dbf5ee609..8d232f3357a1fcbd16b24781d72109666f4fa37d 100644 (file)
--- a/libs/ezsat/ezsat.cc
+++ b/libs/ezsat/ezsat.cc
@@ -1096,7 +1096,7 @@ std::vector<int> ezSAT::vec_shift_right(const std::vector<int> &vec1, const std:
 std::vector<int> ezSAT::vec_shift_left(const std::vector<int> &vec1, const std::vector<int> &vec2, bool vec2_signed, int extend_left, int extend_right)
 {
        // vec2_signed is not implemented in vec_shift_left() yet
-       assert(vec2_signed == false);
+       if (vec2_signed) assert(vec2_signed == false);
 
        int vec2_bits = std::min(my_clog2(vec1.size()), int(vec2.size()));
 

diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index 7ab50991d872685240eebac622f03fa8b9f17c11..3133cb2a63129bb3270888e5c94135a710c19447 100644 (file)
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -1061,7 +1061,9 @@ struct ShareWorker
        ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) :
                        config(config), design(design), module(module), mi(module)
        {
+       #ifndef NDEBUG
                bool before_scc = module_has_scc();
+       #endif
 
                generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end());
                generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end());
@@ -1355,8 +1357,10 @@ struct ShareWorker
 
                log_assert(recursion_state.empty());
 
+       #ifndef NDEBUG
                bool after_scc = before_scc || module_has_scc();
                log_assert(before_scc == after_scc);
+       #endif
        }
 };
 

diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index cc6f97c7e991cbc9e8cf7a4004e6e2a42a953c01..b0318a0b33a5059f892f464fd1e10ca0def19e5f 100644 (file)
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -365,8 +365,12 @@ static void map_sr_to_arst(const char *from, const char *to)
        if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
                return;
 
-       char from_clk_pol = from[8], from_set_pol = from[9], from_clr_pol = from[10];
-       char to_clk_pol = to[6], to_rst_pol = to[7], to_rst_val = to[8];
+       char from_clk_pol YS_ATTRIBUTE(unused) = from[8];
+       char from_set_pol = from[9];
+       char from_clr_pol = from[10];
+       char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
+       char to_rst_pol YS_ATTRIBUTE(unused) = to[7];
+       char to_rst_val = to[8];
 
        log_assert(from_clk_pol == to_clk_pol);
        log_assert(to_rst_pol == from_set_pol && to_rst_pol == from_clr_pol);

diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc
index 853339b955280f74e6d4e60d37262de9812561ab..753fa7bf2576ddbdbea4cafc384cfb55a327a179 100644 (file)
--- a/passes/tests/test_abcloop.cc
+++ b/passes/tests/test_abcloop.cc
@@ -132,7 +132,7 @@ static void test_abcloop()
                SatGen satgen(&ez, &sigmap);
 
                for (auto c : module->cells()) {
-                       bool ok = satgen.importCell(c);
+                       bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
                        log_assert(ok);
                }
 
@@ -182,7 +182,7 @@ static void test_abcloop()
        SatGen satgen(&ez, &sigmap);
 
        for (auto c : module->cells()) {
-               bool ok = satgen.importCell(c);
+               bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
                log_assert(ok);
        }