add fishmv fmvis addpcis instructions to test_pysvp64dis.py

these are not hugely verbose

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 2566d944da26d28c54671ca9aff18b9dfde57fed..daec78c85114ec52cdb0ac12b5e23e9e92c7b8d3 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -7,9 +7,7 @@ import sys
 
 class SVSTATETestCase(unittest.TestCase):
 
-    def test_0_addi(self):
-        expected = ['addi 1,5,2',
-                        ]
+    def _do_tst(self, expected):
         isa = SVP64Asm(expected)
         lst = list(isa)
         with Program(lst, bigendian=False) as program:
@@ -28,27 +26,25 @@ class SVSTATETestCase(unittest.TestCase):
                                      "instruction does not match "
                                      "'%s' expected '%s'" % (line, expected[i]))
 
+
+    def test_0_addi(self):
+        expected = ['addi 1,5,2',
+                        ]
+        self._do_tst(expected)
+
     def test_1_svshape2(self):
         expected = [
                     'svshape2 12,1,15,5,0,0'
                         ]
-        isa = SVP64Asm(expected)
-        lst = list(isa)
-        with Program(lst, bigendian=False) as program:
-            print ("ops", program._instructions)
-            program.binfile.seek(0)
-            insns = load(program.binfile)
-            #for insn in insns:
-                #print ("insn", insn)
-            insns = list(insns)
-            print ("insns", insns)
-            for i, line in enumerate(dump(insns, verbosity=Verbosity.SHORT)):
-                name = expected[i].split(" ")[0]
-                with self.subTest(name):
-                    print("instruction", repr(line), repr(expected[i]))
-                    self.assertEqual(expected[i], line,
-                                     "instruction does not match "
-                                     "'%s' expected '%s'" % (line, expected[i]))
+        self._do_tst(expected)
+
+    def test_2_d_custom_op(self):
+        expected = [
+                    'addpcis 12,5',
+                    'fishmv 12,2',
+                    'fmvis 12,97',
+                        ]
+        self._do_tst(expected)
 
 if __name__ == "__main__":
     unittest.main()