adding call out to cpu_memory_interface verilog module in cpu.py

diff --git a/README.txt b/README.txt
new file mode 100644 (file)
index 0000000..611dc57
--- /dev/null
+++ b/README.txt
@@ -0,0 +1,6 @@
+# Limitations
+
+* there is no << or >> operator, only <<< and >>> (arithmetic shift)
+* it is not possible to declare parameters
+* an input of [31:2] is not possible, only a parameter of [N:0]
+

diff --git a/cpu.py b/cpu.py
index 9fa8596f008c55e0e0d1a7889191fb4f0af3c3c4..98e888ab20fbe2f5edf9c86179340158b13e8999 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -37,23 +37,102 @@ class CPU(Module):
     """
 
     def __init__(self):
-        self.instruction = Signal(32)
-        self.funct7 = Signal(7)
-        self.funct3 = Signal(3)
-        self.rd = Signal(5)
-        self.rs1 = Signal(5)
-        self.rs2 = Signal(5)
-        self.immediate = Signal(32)
-        self.opcode = Signal(7)
-        self.decode_action = Signal(decode_action)
+        #self.clk = ClockSignal()
+        #self.reset = ResetSignal()
+        self.tty_write = Signal()
+        self.tty_write_data = Signal(8)
+        self.tty_write_busy = Signal()
+        self.switch_2 = Signal()
+        self.switch_3 = Signal()
+        self.led_1 = Signal()
+        self.led_3 = Signal()
+
+        ram_size = Constant(0x8000)
+        ram_start = Constant(0x10000, 32)
+        reset_vector = Signal(32)
+        mtvec = Signal(32)
+
+        reset_vector.eq(ram_start)
+        mtvec.eq(ram_start + 0x40)
+
+        l = []
+        for i in range(31):
+            l.append(Signal(32, name="register%d" % i))
+        self.registers = Array(l)
+
+        #self.sync += self.registers[0].eq(0)
+        #self.sync += self.registers[1].eq(0)
+
+        memory_interface_fetch_address = Signal(32)[2:]
+        memory_interface_fetch_data = Signal(32)
+        memory_interface_fetch_valid = Signal()
+        memory_interface_rw_address= Signal(32)[2:]
+        memory_interface_rw_byte_mask = Signal(4)
+        memory_interface_rw_read_not_write = Signal()
+        memory_interface_rw_active = Signal()
+        memory_interface_rw_data_in = Signal(32)
+        memory_interface_rw_data_out = Signal(32)
+        memory_interface_rw_address_valid = Signal()
+        memory_interface_rw_wait = Signal()
+
+        mi = Instance("cpu_memory_interface",
+                    p_ram_size = ram_size,
+                    p_ram_start = ram_start,
+                    i_clk=ClockSignal(),
+                    i_rst=ResetSignal(),
+                    i_fetch_address = memory_interface_fetch_address,
+                    o_fetch_data = memory_interface_fetch_data,
+                    o_fetch_valid = memory_interface_fetch_valid,
+                    i_rw_address = memory_interface_rw_address,
+                    i_rw_byte_mask = memory_interface_rw_byte_mask,
+                    i_rw_read_not_write = memory_interface_rw_read_not_write,
+                    i_rw_active = memory_interface_rw_active,
+                    i_rw_data_in = memory_interface_rw_data_in,
+                    o_rw_data_out = memory_interface_rw_data_out,
+                    o_rw_address_valid = memory_interface_rw_address_valid,
+                    o_rw_wait = memory_interface_rw_wait,
+                    o_tty_write = self.tty_write,
+                    o_tty_write_data = self.tty_write_data,
+                    i_tty_write_busy = self.tty_write_busy,
+                    i_switch_2 = self.switch_2,
+                    i_switch_3 = self.switch_3,
+                    o_led_1 = self.led_1,
+                    o_led_3 = self.led_3
+                  )
+        self.specials += mi
 
+"""
+    cpu_memory_interface #(
+        .ram_size(ram_size),
+        .ram_start(ram_start)
+        ) memory_interface(
+        .clk(clk),
+        .reset(reset),
+        .fetch_address(memory_interface_fetch_address),
+        .fetch_data(memory_interface_fetch_data),
+        .fetch_valid(memory_interface_fetch_valid),
+        .rw_address(memory_interface_rw_address),
+        .rw_byte_mask(memory_interface_rw_byte_mask),
+        .rw_read_not_write(memory_interface_rw_read_not_write),
+        .rw_active(memory_interface_rw_active),
+        .rw_data_in(memory_interface_rw_data_in),
+        .rw_data_out(memory_interface_rw_data_out),
+        .rw_address_valid(memory_interface_rw_address_valid),
+        .rw_wait(memory_interface_rw_wait),
+        .tty_write(tty_write),
+        .tty_write_data(tty_write_data),
+        .tty_write_busy(tty_write_busy),
+        .switch_2(switch_2),
+        .switch_3(switch_3),
+        .led_1(led_1),
+        .led_3(led_3)
+        );
+"""
 
 if __name__ == "__main__":
-    example = CPUDecoder()
+    example = CPU()
     print(verilog.convert(example,
          {
-           example.clk,
-           example.reset,
            example.tty_write,
            example.tty_write_data,
            example.tty_write_busy,

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index 820591efa2ab76c723b357712ab51f14aa192c69..f3269fb75a9fe890c5e11c9be55c2f7bdcce3e39 100644 (file)
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -29,8 +29,6 @@ from migen.fhdl import verilog
 #from riscvdefs import *
 from cpudefs import *
 
-reset_vector = 0x0 #32'hXXXXXXXX;
-mtvec = 0x0 # 32'hXXXXXXXX;
 
 class CPUFetchStage(Module):
     def __init__(self):
@@ -47,6 +45,8 @@ class CPUFetchStage(Module):
         self.output_instruction = Signal(32)
         self.output_state = Signal(fetch_output_state,
                                    reset=fetch_output_state_empty)
+        self.reset_vector = Signal(32) #32'hXXXXXXXX; - parameter
+        self.mtvec = Signal(32) # 32'hXXXXXXXX; - parameter
 
         #self.comb += [
         #    self.cd_sys.clk.eq(self.clk),
@@ -121,4 +121,7 @@ if __name__ == "__main__":
            example.target_pc,
            example.output_pc,
            example.output_instruction,
-           example.output_state }))
+           example.output_state
+           example.reset_vector,
+           example.mtvec
+            }))