program->shader.selector = &sel;
program->shader.is_monolithic = true;
program->uses_grid_size = sel.info.uses_grid_size;
- program->uses_block_size = sel.info.uses_block_size;
program->uses_bindless_samplers = sel.info.uses_bindless_samplers;
program->uses_bindless_images = sel.info.uses_bindless_images;
- program->variable_group_size =
+ program->reads_variable_block_size =
+ sel.info.uses_block_size &&
sel.info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
void *ir_binary = si_get_ir_binary(&sel);
bool scratch_enabled = shader->config.scratch_bytes_per_wave > 0;
unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS +
(sel.info.uses_grid_size ? 3 : 0) +
- (sel.info.uses_block_size ? 3 : 0);
+ (program->reads_variable_block_size ? 3 : 0);
shader->config.rsrc1 =
S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) |
radeon_emit(cs, info->grid[1]);
radeon_emit(cs, info->grid[2]);
}
- if (program->variable_group_size && program->uses_block_size) {
+ if (program->reads_variable_block_size) {
radeon_set_sh_reg_seq(cs, block_size_reg, 3);
radeon_emit(cs, info->block[0]);
radeon_emit(cs, info->block[1]);
struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS];
unsigned use_code_object_v2 : 1;
- unsigned variable_group_size : 1;
unsigned uses_grid_size:1;
- unsigned uses_block_size:1;
unsigned uses_bindless_samplers:1;
unsigned uses_bindless_images:1;
+ bool reads_variable_block_size;
};
void si_destroy_compute(struct si_compute *program);
declare_per_stage_desc_pointers(ctx, &fninfo, true);
if (shader->selector->info.uses_grid_size)
add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
- if (shader->selector->info.uses_block_size)
+ if (shader->selector->info.uses_block_size &&
+ shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
for (i = 0; i < 3; i++) {