AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile);
void loadState(CheckpointIn &cp) override;
- void initState();
+ void initState() override;
void argsInit(int intSize, int pageSize);
public:
- AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
+ AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override;
/// Explicitly import the otherwise hidden getSyscallArg
using LiveProcess::getSyscallArg;
- void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val);
- void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
+ void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val) override;
+ void setSyscallReturn(ThreadContext *tc,
+ SyscallReturn return_value) override;
};
/* No architectural page table defined for this ISA */
/**
* Initialise the state of the system.
*/
- virtual void initState();
+ void initState() override;
/**
* Serialization stuff
/** Override startup() to provide a path to call setupFuncEvents()
*/
- virtual void startup();
+ void startup() override;
/**
* Set the m5AlphaAccess pointer in the console
return addFuncEvent<T>(consoleSymtab, lbl);
}
- virtual Addr fixFuncEventAddr(Addr addr);
+ Addr fixFuncEventAddr(Addr addr) override;
public:
void setIntrFreq(Tick freq) { intrFreq = freq; }
TLB(const Params *p);
virtual ~TLB();
- void takeOverFrom(BaseTLB *otlb) {}
+ void takeOverFrom(BaseTLB *otlb) override {}
- virtual void regStats();
+ void regStats() override;
int getsize() const { return table.size(); }
TlbEntry &index(bool advance = true);
void insert(Addr vaddr, TlbEntry &entry);
- void flushAll();
+ void flushAll() override;
void flushProcesses();
void flushAddr(Addr addr, uint8_t asn);
void
- demapPage(Addr vaddr, uint64_t asn)
+ demapPage(Addr vaddr, uint64_t asn) override
{
assert(asn < (1 << 8));
flushAddr(vaddr, asn);
return dynamic_cast<const Params *>(_params);
}
- virtual void init();
+ void init() override;
bool haveLPAE() const { return _haveLPAE; }
bool haveVirtualization() const { return _haveVirtualization; }
/** Checks if all state is cleared and if so, completes drain */
void completeDrain();
DrainState drain() override;
- virtual void drainResume() override;
+ void drainResume() override;
- virtual BaseMasterPort& getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ BaseMasterPort& getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID) override;
- void regStats();
+ void regStats() override;
Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid,
bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
virtual ~TLB();
- void takeOverFrom(BaseTLB *otlb);
+ void takeOverFrom(BaseTLB *otlb) override;
/// setup all the back pointers
- virtual void init();
+ void init() override;
TableWalker *getTableWalker() { return tableWalker; }
/** Reset the entire TLB. Used for CPU switching to prevent stale
* translations after multiple switches
*/
- void flushAll()
+ void flushAll() override
{
flushAllSecurity(false, 0, true);
flushAllSecurity(true, 0, true);
void printTlb() const;
- void demapPage(Addr vaddr, uint64_t asn)
+ void demapPage(Addr vaddr, uint64_t asn) override
{
// needed for x86 only
panic("demapPage() is not implemented.\n");
}
- static bool validVirtualAddress(Addr vaddr);
-
/**
* Do a functional lookup on the TLB (for debugging)
* and don't modify any internal state
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
- void regStats();
+ void regStats() override;
void regProbePoints() override;
*
* @return A pointer to the walker master port
*/
- virtual BaseMasterPort* getMasterPort();
+ BaseMasterPort* getMasterPort() override;
// Caching misc register values here.
// Writing to misc registers needs to invalidate them.
{}
public:
- void demapPage(Addr vaddr, uint64_t asn);
+ void demapPage(Addr vaddr, uint64_t asn) override;
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
* @return a reference to the port with the given name
*/
BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ PortID idx = InvalidPortID) override;
/** Get cpu task id */
uint32_t taskId() const { return _taskId; }
BaseCPU(Params *params, bool is_checker = false);
virtual ~BaseCPU();
- virtual void init();
- virtual void startup();
- virtual void regStats();
+ void init() override;
+ void startup() override;
+ void regStats() override;
void regProbePoints() override;
/** id attached to all issued requests */
MasterID masterId;
public:
- virtual void init();
+ void init() override;
typedef CheckerCPUParams Params;
CheckerCPU(Params *p);
void setDcachePort(MasterPort *dcache_port);
- MasterPort &getDataPort()
+ MasterPort &getDataPort() override
{
// the checker does not have ports on its own so return the
// data port of the actual CPU core
return *dcachePort;
}
- MasterPort &getInstPort()
+ MasterPort &getInstPort() override
{
// the checker does not have ports on its own so return the
// data port of the actual CPU core
TheISA::TLB* getITBPtr() { return itb; }
TheISA::TLB* getDTBPtr() { return dtb; }
- virtual Counter totalInsts() const
+ virtual Counter totalInsts() const override
{
return 0;
}
- virtual Counter totalOps() const
+ virtual Counter totalOps() const override
{
return 0;
}
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
- void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
- Addr getEA() const { panic("SimpleCPU::getEA() not implemented\n"); }
+ void setEA(Addr EA) override
+ { panic("CheckerCPU::setEA() not implemented\n"); }
+ Addr getEA() const override
+ { panic("CheckerCPU::getEA() not implemented\n"); }
// The register accessor methods provide the index of the
// instruction's operand (e.g., 0 or 1), not the architectural
// storage (which is pretty hard to imagine they would have reason
// to do).
- IntReg readIntRegOperand(const StaticInst *si, int idx)
+ IntReg readIntRegOperand(const StaticInst *si, int idx) override
{
return thread->readIntReg(si->srcRegIdx(idx));
}
- FloatReg readFloatRegOperand(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
return thread->readFloatReg(reg_idx);
}
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si,
+ int idx) override
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
return thread->readFloatRegBits(reg_idx);
}
- CCReg readCCRegOperand(const StaticInst *si, int idx)
+ CCReg readCCRegOperand(const StaticInst *si, int idx) override
{
int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
return thread->readCCReg(reg_idx);
result.push(instRes);
}
- void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
+ void setIntRegOperand(const StaticInst *si, int idx,
+ IntReg val) override
{
thread->setIntReg(si->destRegIdx(idx), val);
setResult<uint64_t>(val);
}
- void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx,
+ FloatReg val) override
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
thread->setFloatReg(reg_idx, val);
}
void setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val)
+ FloatRegBits val) override
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
thread->setFloatRegBits(reg_idx, val);
setResult<uint64_t>(val);
}
- void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
+ void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
{
int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
thread->setCCReg(reg_idx, val);
setResult<uint64_t>(val);
}
- bool readPredicate() { return thread->readPredicate(); }
- void setPredicate(bool val)
+ bool readPredicate() override { return thread->readPredicate(); }
+ void setPredicate(bool val) override
{
thread->setPredicate(val);
}
- TheISA::PCState pcState() const { return thread->pcState(); }
- void pcState(const TheISA::PCState &val)
+ TheISA::PCState pcState() const override { return thread->pcState(); }
+ void pcState(const TheISA::PCState &val) override
{
DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
val, thread->pcState());
return thread->readMiscRegNoEffect(misc_reg);
}
- MiscReg readMiscReg(int misc_reg)
+ MiscReg readMiscReg(int misc_reg) override
{
return thread->readMiscReg(misc_reg);
}
return thread->setMiscRegNoEffect(misc_reg, val);
}
- void setMiscReg(int misc_reg, const MiscReg &val)
+ void setMiscReg(int misc_reg, const MiscReg &val) override
{
DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg);
miscRegIdxs.push(misc_reg);
return thread->setMiscReg(misc_reg, val);
}
- MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+ MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
{
int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
return thread->readMiscReg(reg_idx);
}
- void setMiscRegOperand(
- const StaticInst *si, int idx, const MiscReg &val)
+ void setMiscRegOperand(const StaticInst *si, int idx,
+ const MiscReg &val) override
{
int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
return this->setMiscReg(reg_idx, val);
newPCState = val;
}
- void demapPage(Addr vaddr, uint64_t asn)
+ void demapPage(Addr vaddr, uint64_t asn) override
{
this->itb->demapPage(vaddr, asn);
this->dtb->demapPage(vaddr, asn);
}
// monitor/mwait funtions
- virtual void armMonitor(Addr address) { BaseCPU::armMonitor(0, address); }
- bool mwait(PacketPtr pkt) { return BaseCPU::mwait(0, pkt); }
- void mwaitAtomic(ThreadContext *tc)
+ void armMonitor(Addr address) override
+ { BaseCPU::armMonitor(0, address); }
+ bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); }
+ void mwaitAtomic(ThreadContext *tc) override
{ return BaseCPU::mwaitAtomic(0, tc, thread->dtb); }
- AddressMonitor *getAddrMonitor() { return BaseCPU::getCpuAddrMonitor(0); }
+ AddressMonitor *getAddrMonitor() override
+ { return BaseCPU::getCpuAddrMonitor(0); }
void demapInstPage(Addr vaddr, uint64_t asn)
{
this->dtb->demapPage(vaddr, asn);
}
- Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size,
+ unsigned flags) override;
Fault writeMem(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Addr addr, unsigned flags, uint64_t *res) override;
- unsigned int readStCondFailures() const {
+ unsigned int readStCondFailures() const override {
return thread->readStCondFailures();
}
- void setStCondFailures(unsigned int sc_failures)
+ void setStCondFailures(unsigned int sc_failures) override
{}
/////////////////////////////////////////////////////
- Fault hwrei() { return thread->hwrei(); }
- bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
+ Fault hwrei() override { return thread->hwrei(); }
+ bool simPalCheck(int palFunc) override
+ { return thread->simPalCheck(palFunc); }
void wakeup(ThreadID tid) override { }
// Assume that the normal CPU's call to syscall was successful.
// The checker's state would have already been updated by the syscall.
- void syscall(int64_t callnum) { }
+ void syscall(int64_t callnum) override { }
void handleError()
{
void dumpAndExit();
- ThreadContext *tcBase() { return tc; }
+ ThreadContext *tcBase() override { return tc; }
SimpleThread *threadBase() { return thread; }
Result unverifiedResult;
protected:
/** Return a reference to the data port. */
- MasterPort &getDataPort();
+ MasterPort &getDataPort() override;
/** Return a reference to the instruction port. */
- MasterPort &getInstPort();
+ MasterPort &getInstPort() override;
public:
MinorCPU(MinorCPUParams *params);
public:
/** Starting, waking and initialisation */
- void init();
- void startup();
+ void init() override;
+ void startup() override;
void wakeup(ThreadID tid) override;
Addr dbg_vtophys(Addr addr);
Minor::MinorStats stats;
/** Stats interface from SimObject (by way of BaseCPU) */
- void regStats();
+ void regStats() override;
/** Simple inst count interface from BaseCPU */
- Counter totalInsts() const;
- Counter totalOps() const;
+ Counter totalInsts() const override;
+ Counter totalOps() const override;
void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
/** Serialize pipeline data */
- void serialize(CheckpointOut &cp) const;
- void unserialize(CheckpointIn &cp);
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/** Drain interface */
DrainState drain() override;
/** Signal from Pipeline that MinorCPU should signal that a drain
* is complete and set its drainState */
void signalDrainDone();
- void memWriteback();
+ void memWriteback() override;
/** Switching interface from BaseCPU */
- void switchOut();
- void takeOverFrom(BaseCPU *old_cpu);
+ void switchOut() override;
+ void takeOverFrom(BaseCPU *old_cpu) override;
/** Thread activation interface from BaseCPU. */
- void activateContext(ThreadID thread_id);
- void suspendContext(ThreadID thread_id);
+ void activateContext(ThreadID thread_id) override;
+ void suspendContext(ThreadID thread_id) override;
/** Interface for stages to signal that they have become active after
* a callback or eventq event where the pipeline itself may have
"Found extra timing match (pattern %d '%s')"
" %s %16x (type %s)\n",
i, timing.description, inst->disassemble(0), mach_inst,
- typeid(*inst).name());
+ typeid(inst).name());
return &timing;
}
/** A custom evaluate allows report in the right place (between
* stages and pipeline advance) */
- void evaluate();
+ void evaluate() override;
void countCycles(Cycles delta) override
{
~FullO3CPU();
/** Registers statistics. */
- void regStats();
+ void regStats() override;
ProbePointArg<PacketPtr> *ppInstAccessComplete;
ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
/** Register probe points. */
- void regProbePoints();
+ void regProbePoints() override;
void demapPage(Addr vaddr, uint64_t asn)
{
void tick();
/** Initialize the CPU */
- void init();
+ void init() override;
- void startup();
+ void startup() override;
/** Returns the Number of Active Threads in the CPU */
int numActiveThreads()
void removeThread(ThreadID tid);
/** Count the Total Instructions Committed in the CPU. */
- virtual Counter totalInsts() const;
+ Counter totalInsts() const override;
/** Count the Total Ops (including micro ops) committed in the CPU. */
- virtual Counter totalOps() const;
+ Counter totalOps() const override;
/** Add Thread to Active Threads List. */
- void activateContext(ThreadID tid);
+ void activateContext(ThreadID tid) override;
/** Remove Thread from Active Threads List */
- void suspendContext(ThreadID tid);
+ void suspendContext(ThreadID tid) override;
/** Remove Thread from Active Threads List &&
* Remove Thread Context from CPU.
*/
- void haltContext(ThreadID tid);
+ void haltContext(ThreadID tid) override;
/** Update The Order In Which We Process Threads. */
void updateThreadPriority();
void commitDrained(ThreadID tid);
/** Switches out this CPU. */
- virtual void switchOut();
+ void switchOut() override;
/** Takes over from another CPU. */
- virtual void takeOverFrom(BaseCPU *oldCPU);
+ void takeOverFrom(BaseCPU *oldCPU) override;
- void verifyMemoryMode() const;
+ void verifyMemoryMode() const override;
/** Get the current instruction sequence number, and increment it. */
InstSeqNum getAndIncrementInstSeq()
/** Halts the CPU. */
void halt() { panic("Halt not implemented!\n"); }
- /** Check if this address is a valid instruction address. */
- bool validInstAddr(Addr addr) { return true; }
-
- /** Check if this address is a valid data address. */
- bool validDataAddr(Addr addr) { return true; }
-
/** Register accessors. Index refers to the physical register index. */
/** Reads a miscellaneous register. */
}
/** Used by the fetch unit to get a hold of the instruction port. */
- virtual MasterPort &getInstPort() { return icachePort; }
+ MasterPort &getInstPort() override { return icachePort; }
/** Get the dcache port (used to find block size for translations). */
- virtual MasterPort &getDataPort() { return dcachePort; }
+ MasterPort &getDataPort() override { return dcachePort; }
/** Stat for total number of times the CPU is descheduled. */
Stats::Scalar timesIdled;
/**
* Registers statistics.
*/
- void regStats();
+ void regStats() override;
void regProbePoints() override;
AtomicSimpleCPU(AtomicSimpleCPUParams *params);
virtual ~AtomicSimpleCPU();
- virtual void init();
+ void init() override;
private:
protected:
/** Return a reference to the data port. */
- virtual MasterPort &getDataPort() { return dcachePort; }
+ MasterPort &getDataPort() override { return dcachePort; }
/** Return a reference to the instruction port. */
- virtual MasterPort &getInstPort() { return icachePort; }
+ MasterPort &getInstPort() override { return icachePort; }
/** Perform snoop for other cpu-local thread contexts. */
void threadSnoop(PacketPtr pkt, ThreadID sender);
DrainState drain() override;
void drainResume() override;
- void switchOut();
- void takeOverFrom(BaseCPU *oldCPU);
+ void switchOut() override;
+ void takeOverFrom(BaseCPU *oldCPU) override;
- void verifyMemoryMode() const;
+ void verifyMemoryMode() const override;
- virtual void activateContext(ThreadID thread_num);
- virtual void suspendContext(ThreadID thread_num);
+ void activateContext(ThreadID thread_num) override;
+ void suspendContext(ThreadID thread_num) override;
- Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size,
+ unsigned flags) override;
Fault writeMem(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Addr addr, unsigned flags, uint64_t *res) override;
- virtual void regProbePoints();
+ void regProbePoints() override;
/**
* Print state of address in memory system via PrintReq (for
BaseSimpleCPU(BaseSimpleCPUParams *params);
virtual ~BaseSimpleCPU();
void wakeup(ThreadID tid) override;
- virtual void init();
+ void init() override;
public:
Trace::InstRecord *traceData;
CheckerCPU *checker;
void postExecute();
void advancePC(const Fault &fault);
- virtual void haltContext(ThreadID thread_num);
+ void haltContext(ThreadID thread_num) override;
// statistics
- virtual void regStats();
- virtual void resetStats();
+ void regStats() override;
+ void resetStats() override;
- virtual void startup();
+ void startup() override;
virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
unsigned flags) = 0;
unsigned flags, uint64_t* res) = 0;
void countInst();
- virtual Counter totalInsts() const;
- virtual Counter totalOps() const;
+ Counter totalInsts() const override;
+ Counter totalOps() const override;
void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
TimingSimpleCPU(TimingSimpleCPUParams * params);
virtual ~TimingSimpleCPU();
- virtual void init();
+ void init() override;
private:
protected:
/** Return a reference to the data port. */
- virtual MasterPort &getDataPort() { return dcachePort; }
+ MasterPort &getDataPort() override { return dcachePort; }
/** Return a reference to the instruction port. */
- virtual MasterPort &getInstPort() { return icachePort; }
+ MasterPort &getInstPort() override { return icachePort; }
public:
DrainState drain() override;
void drainResume() override;
- void switchOut();
- void takeOverFrom(BaseCPU *oldCPU);
+ void switchOut() override;
+ void takeOverFrom(BaseCPU *oldCPU) override;
- void verifyMemoryMode() const;
+ void verifyMemoryMode() const override;
- virtual void activateContext(ThreadID thread_num);
- virtual void suspendContext(ThreadID thread_num);
+ void activateContext(ThreadID thread_num) override;
+ void suspendContext(ThreadID thread_num) override;
- Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size,
+ unsigned flags) override;
Fault writeMem(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Addr addr, unsigned flags, uint64_t *res) override;
void fetch();
void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
~TrafficGen() {}
- virtual BaseMasterPort& getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ BaseMasterPort& getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID) override;
- void init();
+ void init() override;
- void initState();
+ void initState() override;
DrainState drain() override;
void unserialize(CheckpointIn &cp) override;
/** Register statistics */
- void regStats();
+ void regStats() override;
};
return dynamic_cast<const Params *>(_params);
}
- virtual void startup();
+ void startup() override;
/**
* memory mapped reads and writes
*/
- virtual Tick read(PacketPtr pkt);
- virtual Tick write(PacketPtr pkt);
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
/**
* standard serialization routines for checkpointing
int intr_sum_type[Tsunami::Max_CPUs];
int ipi_pending[Tsunami::Max_CPUs];
- void init();
+ void init() override;
public:
typedef TsunamiParams Params;
/**
* Cause the cpu to post a serial interrupt to the CPU.
*/
- virtual void postConsoleInt();
+ void postConsoleInt() override;
/**
* Clear a posted CPU interrupt (id=55)
*/
- virtual void clearConsoleInt();
+ void clearConsoleInt() override;
/**
* Cause the chipset to post a cpi interrupt to the CPU.
*/
- virtual void postPciInt(int line);
+ void postPciInt(int line) override;
/**
* Clear a posted PCI->CPU interrupt
*/
- virtual void clearPciInt(int line);
+ void clearPciInt(int line) override;
- virtual Addr pciToDma(Addr pciAddr) const;
+ Addr pciToDma(Addr pciAddr) const override;
/**
* Calculate the configuration address given a bus/dev/func.
*/
- virtual Addr calcPciConfigAddr(int bus, int dev, int func);
+ Addr calcPciConfigAddr(int bus, int dev, int func) override;
/**
* Calculate the address for an IO location on the PCI bus.
*/
- virtual Addr calcPciIOAddr(Addr addr);
+ Addr calcPciIOAddr(Addr addr) override;
/**
* Calculate the address for a memory location on the PCI bus.
*/
- virtual Addr calcPciMemAddr(Addr addr);
+ Addr calcPciMemAddr(Addr addr) override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
return dynamic_cast<const Params *>(_params);
}
- virtual Tick read(PacketPtr pkt);
+ Tick read(PacketPtr pkt) override;
- virtual Tick write(PacketPtr pkt);
+ Tick write(PacketPtr pkt) override;
/**
* post an RTC interrupt to the CPU
return dynamic_cast<const Params *>(_params);
}
- virtual Tick read(PacketPtr pkt);
- virtual Tick write(PacketPtr pkt);
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
/**
* Post an PIC interrupt to the CPU via the CChip
/**
* Start running.
*/
- virtual void startup();
+ void startup() override;
};
Addr calcIOAddr(Addr addr);
Addr calcMemAddr(Addr addr);
- virtual Tick read(PacketPtr pkt);
- virtual Tick write(PacketPtr pkt);
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
CopyEngine(const Params *params);
~CopyEngine();
- void regStats();
+ void regStats() override;
- virtual BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ BaseMasterPort &getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID) override;
- virtual Tick read(PacketPtr pkt);
- virtual Tick write(PacketPtr pkt);
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
- virtual std::streampos size() const;
+ std::streampos size() const override;
- virtual std::streampos read(uint8_t *data, std::streampos offset) const;
- virtual std::streampos write(const uint8_t *data, std::streampos offset);
+ std::streampos read(uint8_t *data, std::streampos offset) const override;
+ std::streampos write(const uint8_t *data, std::streampos offset) override;
};
void SafeRead(std::ifstream &stream, void *data, int count);
protected:
- bool recvTimingResp(PacketPtr pkt);
- void recvReqRetry() ;
+ bool recvTimingResp(PacketPtr pkt) override;
+ void recvReqRetry() override;
void queueDma(PacketPtr pkt);
bool dmaPending() const { return dmaPort.dmaPending(); }
- virtual void init();
+ void init() override;
unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
- virtual BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ BaseMasterPort &getMasterPort(const std::string &if_name,
+ PortID idx = InvalidPortID) override;
};
return dynamic_cast<const Params *>(_params);
}
- virtual EtherInt *getEthPort(const std::string &if_name, int idx);
+ EtherInt *getEthPort(const std::string &if_name, int idx) override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
return dynamic_cast<const Params *>(_params);
}
- virtual EtherInt *getEthPort(const std::string &if_name, int idx);
+ EtherInt *getEthPort(const std::string &if_name, int idx) override;
virtual bool recvPacket(EthPacketPtr packet);
virtual void sendDone();
I2CBus(const I2CBusParams* p);
- virtual Tick read(PacketPtr pkt);
- virtual Tick write(PacketPtr pkt);
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
class RxDescCache : public DescCache<iGbReg::RxDesc>
{
protected:
- virtual Addr descBase() const { return igbe->regs.rdba(); }
- virtual long descHead() const { return igbe->regs.rdh(); }
- virtual long descLen() const { return igbe->regs.rdlen() >> 4; }
- virtual long descTail() const { return igbe->regs.rdt(); }
- virtual void updateHead(long h) { igbe->regs.rdh(h); }
- virtual void enableSm();
- virtual void fetchAfterWb() {
+ Addr descBase() const override { return igbe->regs.rdba(); }
+ long descHead() const override { return igbe->regs.rdh(); }
+ long descLen() const override { return igbe->regs.rdlen() >> 4; }
+ long descTail() const override { return igbe->regs.rdt(); }
+ void updateHead(long h) override { igbe->regs.rdh(h); }
+ void enableSm() override;
+ void fetchAfterWb() override {
if (!igbe->rxTick && igbe->drainState() == DrainState::Running)
fetchDescriptors();
}
EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktHdrEvent;
EventWrapper<RxDescCache, &RxDescCache::pktSplitDone> pktDataEvent;
- virtual bool hasOutstandingEvents();
+ bool hasOutstandingEvents() override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
class TxDescCache : public DescCache<iGbReg::TxDesc>
{
protected:
- virtual Addr descBase() const { return igbe->regs.tdba(); }
- virtual long descHead() const { return igbe->regs.tdh(); }
- virtual long descTail() const { return igbe->regs.tdt(); }
- virtual long descLen() const { return igbe->regs.tdlen() >> 4; }
- virtual void updateHead(long h) { igbe->regs.tdh(h); }
- virtual void enableSm();
- virtual void actionAfterWb();
- virtual void fetchAfterWb() {
+ Addr descBase() const override { return igbe->regs.tdba(); }
+ long descHead() const override { return igbe->regs.tdh(); }
+ long descTail() const override { return igbe->regs.tdt(); }
+ long descLen() const override { return igbe->regs.tdlen() >> 4; }
+ void updateHead(long h) override { igbe->regs.tdh(h); }
+ void enableSm() override;
+ void actionAfterWb() override;
+ void fetchAfterWb() override {
if (!igbe->txTick && igbe->drainState() == DrainState::Running)
fetchDescriptors();
}
completionEnabled = enabled;
}
- virtual bool hasOutstandingEvents();
+ bool hasOutstandingEvents() override;
void nullCallback() {
DPRINTF(EthernetDesc, "Completion writeback complete\n");
IGbE(const Params *params);
~IGbE();
- virtual void init();
+ void init() override;
- virtual EtherInt *getEthPort(const std::string &if_name, int idx);
+ EtherInt *getEthPort(const std::string &if_name, int idx) override;
Tick lastInterrupt;
- virtual Tick read(PacketPtr pkt);
- virtual Tick write(PacketPtr pkt);
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
- virtual Tick writeConfig(PacketPtr pkt);
+ Tick writeConfig(PacketPtr pkt) override;
bool ethRxPkt(EthPacketPtr packet);
void ethTxDone();
void intrPost();
- Tick writeConfig(PacketPtr pkt);
- Tick readConfig(PacketPtr pkt);
+ Tick writeConfig(PacketPtr pkt) override;
+ Tick readConfig(PacketPtr pkt) override;
void setDmaComplete(IdeDisk *disk);
- Tick read(PacketPtr pkt);
- Tick write(PacketPtr pkt);
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
/**
* Register Statistics
*/
- void regStats();
+ void regStats() override;
/**
* Set the controller for this device
NSGigE(Params *params);
~NSGigE();
- virtual EtherInt *getEthPort(const std::string &if_name, int idx);
+ EtherInt *getEthPort(const std::string &if_name, int idx) override;
- virtual Tick writeConfig(PacketPtr pkt);
+ Tick writeConfig(PacketPtr pkt) override;
- virtual Tick read(PacketPtr pkt);
- virtual Tick write(PacketPtr pkt);
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }
protected:
PciDevice *device;
- virtual Tick recvAtomic(PacketPtr pkt);
+ Tick recvAtomic(PacketPtr pkt) override;
- virtual AddrRangeList getAddrRanges() const;
+ AddrRangeList getAddrRanges() const override;
Platform *platform;
*
* @return a list of non-overlapping address ranges
*/
- AddrRangeList getAddrRanges() const;
+ AddrRangeList getAddrRanges() const override;
/**
* Constructor for PCI Dev. This function copies data from the
*/
PciDevice(const Params *params);
- virtual void init();
+ void init() override;
/**
* Serialize this object to the given output stream.
void unserialize(CheckpointIn &cp) override;
- virtual BaseSlavePort &getSlavePort(const std::string &if_name,
- PortID idx = InvalidPortID)
+ BaseSlavePort &getSlavePort(const std::string &if_name,
+ PortID idx = InvalidPortID) override
{
if (if_name == "config") {
return configPort;
public:
bool recvPacket(EthPacketPtr packet);
void transferDone();
- virtual EtherInt *getEthPort(const std::string &if_name, int idx);
+ EtherInt *getEthPort(const std::string &if_name, int idx) override;
/**
* DMA parameters
* Memory Interface
*/
public:
- virtual Tick read(PacketPtr pkt);
- virtual Tick write(PacketPtr pkt);
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
virtual void drainResume() override;
void prepareIO(ContextID cpu, int index);
int _maxVnicDistance;
public:
- virtual void regStats();
- virtual void resetStats();
+ void regStats() override;
+ void resetStats() override;
/**
* Serialization stuff
}
Uart8250(const Params *p);
- virtual Tick read(PacketPtr pkt);
- virtual Tick write(PacketPtr pkt);
- virtual AddrRangeList getAddrRanges() const;
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
+ AddrRangeList getAddrRanges() const override;
/**
* Inform the uart that there is data available.
*/
- virtual void dataAvailable();
+ void dataAvailable() override;
/**
void unserialize(CheckpointIn &cp) override;
protected:
- void recvTMsg(const P9MsgHeader &header, const uint8_t *data, size_t size);
+ void recvTMsg(const P9MsgHeader &header, const uint8_t *data,
+ size_t size) override;
/** Notification of pending data from server */
void serverDataReady();
/**
* Initialise this memory.
*/
- void init();
+ void init() override;
/**
* See if this is a null memory that should never store data and
/**
* Register Statistics
*/
- virtual void regStats();
+ void regStats() override;
};
PacketPtr cleanEvictBlk(CacheBlk *blk);
- void memWriteback();
- void memInvalidate();
- bool isDirty() const;
+ void memWriteback() override;
+ void memInvalidate() override;
+ bool isDirty() const override;
/**
* Cache block visitor that writes back dirty cache blocks using
return tags->findBlock(addr, is_secure);
}
- bool inCache(Addr addr, bool is_secure) const {
+ bool inCache(Addr addr, bool is_secure) const override {
return (tags->findBlock(addr, is_secure) != 0);
}
- bool inMissQueue(Addr addr, bool is_secure) const {
+ bool inMissQueue(Addr addr, bool is_secure) const override {
return (mshrQueue.findMatch(addr, is_secure) != 0);
}
/** Non-default destructor is needed to deallocate memory. */
virtual ~Cache();
- void regStats();
+ void regStats() override;
/** serialize the state of the caches
* We currently don't support checkpointing cache state, so this panics.
* @return The number of sets.
*/
unsigned
- getNumSets() const
+ getNumSets() const override
{
return numSets;
}
* @return The number of ways.
*/
unsigned
- getNumWays() const
+ getNumWays() const override
{
return assoc;
}
* @param way The way of the block.
* @return The cache block.
*/
- CacheBlk *findBlockBySetAndWay(int set, int way) const;
+ CacheBlk *findBlockBySetAndWay(int set, int way) const override;
/**
* Invalidate the given block.
* @param blk The block to invalidate.
*/
- void invalidate(CacheBlk *blk)
+ void invalidate(CacheBlk *blk) override
{
assert(blk);
assert(blk->isValid());
* @return Pointer to the cache block if found.
*/
CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
- int context_src)
+ int context_src) override
{
Addr tag = extractTag(addr);
int set = extractSet(addr);
* @param asid The address space ID.
* @return Pointer to the cache block if found.
*/
- CacheBlk* findBlock(Addr addr, bool is_secure) const;
+ CacheBlk* findBlock(Addr addr, bool is_secure) const override;
/**
* Find an invalid block to evict for the address provided.
* @param addr The addr to a find a replacement candidate for.
* @return The candidate block.
*/
- CacheBlk* findVictim(Addr addr)
+ CacheBlk* findVictim(Addr addr) override
{
BlkType *blk = NULL;
int set = extractSet(addr);
* @param pkt Packet holding the address to update
* @param blk The block to update.
*/
- void insertBlock(PacketPtr pkt, CacheBlk *blk)
+ void insertBlock(PacketPtr pkt, CacheBlk *blk) override
{
Addr addr = pkt->getAddr();
MasterID master_id = pkt->req->masterId();
* Limit the allocation for the cache ways.
* @param ways The maximum number of ways available for replacement.
*/
- virtual void setWayAllocationMax(int ways)
+ virtual void setWayAllocationMax(int ways) override
{
fatal_if(ways < 1, "Allocation limit must be greater than zero");
allocAssoc = ways;
* Get the way allocation mask limit.
* @return The maximum number of ways available for replacement.
*/
- virtual int getWayAllocationMax() const
+ virtual int getWayAllocationMax() const override
{
return allocAssoc;
}
* @param addr The address to get the tag from.
* @return The tag of the address.
*/
- Addr extractTag(Addr addr) const
+ Addr extractTag(Addr addr) const override
{
return (addr >> tagShift);
}
* @param addr The address to get the set from.
* @return The set index of the address.
*/
- int extractSet(Addr addr) const
+ int extractSet(Addr addr) const override
{
return ((addr >> setShift) & setMask);
}
* @param set The set of the block.
* @return The block address.
*/
- Addr regenerateBlkAddr(Addr tag, unsigned set) const
+ Addr regenerateBlkAddr(Addr tag, unsigned set) const override
{
return ((tag << tagShift) | ((Addr)set << setShift));
}
/**
* Called at end of simulation to complete average block reference stats.
*/
- virtual void cleanupRefs();
+ void cleanupRefs() override;
/**
* Print all tags used
*/
- virtual std::string print() const;
+ std::string print() const override;
/**
* Called prior to dumping stats to compute task occupancy
*/
- virtual void computeStats();
+ void computeStats() override;
/**
* Visit each block in the tag store and apply a visitor to the
* Register the stats for this object.
* @param name The name to prepend to the stats name.
*/
- void regStats();
+ void regStats() override;
/**
* Invalidate a cache block.
* @param blk The block to invalidate.
*/
- void invalidate(CacheBlk *blk);
+ void invalidate(CacheBlk *blk) override;
/**
* Access block and update replacement data. May not succeed, in which case
* Just a wrapper of above function to conform with the base interface.
*/
CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat,
- int context_src);
+ int context_src) override;
/**
* Find the block in the cache, do not update the replacement data.
* @param asid The address space ID.
* @return Pointer to the cache block.
*/
- CacheBlk* findBlock(Addr addr, bool is_secure) const;
+ CacheBlk* findBlock(Addr addr, bool is_secure) const override;
/**
* Find a replacement block for the address provided.
* @param pkt The request to a find a replacement candidate for.
* @return The block to place the replacement in.
*/
- CacheBlk* findVictim(Addr addr);
+ CacheBlk* findVictim(Addr addr) override;
- void insertBlock(PacketPtr pkt, CacheBlk *blk);
+ void insertBlock(PacketPtr pkt, CacheBlk *blk) override;
/**
* Return the block size of this cache.
* @return The number of sets.
*/
unsigned
- getNumSets() const
+ getNumSets() const override
{
return 1;
}
* @return The number of ways.
*/
unsigned
- getNumWays() const
+ getNumWays() const override
{
return numBlocks;
}
* @param way The way of the block.
* @return The cache block.
*/
- CacheBlk* findBlockBySetAndWay(int set, int way) const;
+ CacheBlk* findBlockBySetAndWay(int set, int way) const override;
/**
* Align an address to the block size.
* @param addr The address to get the tag from.
* @return The tag.
*/
- Addr extractTag(Addr addr) const
+ Addr extractTag(Addr addr) const override
{
return blkAlign(addr);
}
* @param addr The address to get the set from.
* @return 0.
*/
- int extractSet(Addr addr) const
+ int extractSet(Addr addr) const override
{
return 0;
}
* @param set The set the block belongs to.
* @return the block address.
*/
- Addr regenerateBlkAddr(Addr tag, unsigned set) const
+ Addr regenerateBlkAddr(Addr tag, unsigned set) const override
{
return (tag);
}
/**
* @todo Implement as in lru. Currently not used
*/
- virtual std::string print() const { return ""; }
+ virtual std::string print() const override { return ""; }
/**
* Visit each block in the tag store and apply a visitor to the
public:
- void regStats();
+ void regStats() override;
DRAMCtrl(const DRAMCtrlParams* p);
DrainState drain() override;
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID);
+ PortID idx = InvalidPortID) override;
virtual void init() override;
virtual void startup() override;
DrainState drain() override;
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID);
+ PortID idx = InvalidPortID) override;
- virtual void init();
- virtual void startup();
+ void init() override;
+ void startup() override;
protected:
~FuncPageTable();
- void initState(ThreadContext* tc)
+ void initState(ThreadContext* tc) override
{
}
void map(Addr vaddr, Addr paddr, int64_t size,
- uint64_t flags = 0);
- void remap(Addr vaddr, int64_t size, Addr new_vaddr);
- void unmap(Addr vaddr, int64_t size);
+ uint64_t flags = 0) override;
+ void remap(Addr vaddr, int64_t size, Addr new_vaddr) override;
+ void unmap(Addr vaddr, int64_t size) override;
/**
* Check if any pages in a region are already allocated
* @param size The length of the region.
* @return True if no pages in the region are mapped.
*/
- bool isUnmapped(Addr vaddr, int64_t size);
+ bool isUnmapped(Addr vaddr, int64_t size) override;
/**
* Lookup function
* @param vaddr The virtual address.
* @return entry The page table entry corresponding to vaddr.
*/
- bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
+ bool lookup(Addr vaddr, TheISA::TlbEntry &entry) override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
"virtual channels per virtual network")
virt_nets = Param.Int(Parent.number_of_virtual_networks,
"number of virtual networks")
- channel_width = Param.Int(Parent.bandwidth_factor,
- "channel width == bw factor")
class CreditLink_d(NetworkLink_d):
type = 'CreditLink_d'
NetworkLink_d::NetworkLink_d(const Params *p)
: ClockedObject(p), Consumer(this), m_id(p->link_id),
- m_latency(p->link_latency), channel_width(p->channel_width),
+ m_latency(p->link_latency),
linkBuffer(new flitBuffer_d()), link_consumer(nullptr),
link_srcQueue(nullptr), m_link_utilized(0),
m_vc_load(p->vcs_per_vnet * p->virt_nets)
private:
const int m_id;
const Cycles m_latency;
- const int channel_width;
flitBuffer_d *linkBuffer;
Consumer *link_consumer;
public:
typedef RubyMemoryControlParams Params;
RubyMemoryControl(const Params *p);
- void init();
+ void init() override;
void reset();
~RubyMemoryControl();
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID);
+ PortID idx = InvalidPortID) override;
DrainState drain() override;
- void wakeup();
+ void wakeup() override;
void setDescription(const std::string& name) { m_description = name; };
std::string getDescription() { return m_description; };
void enqueueMemRef(MemoryNode *memRef);
bool areNSlotsAvailable(int n) { return true; }; // infinite queue length
- void print(std::ostream& out) const;
- void regStats();
+ void print(std::ostream& out) const override;
+ void regStats() override;
const int getBank(const Addr addr) const;
const int getRank(const Addr addr) const;
public:
typedef DMASequencerParams Params;
DMASequencer(const Params *);
- void init();
+ void init() override;
RubySystem *m_ruby_system;
public:
};
BaseSlavePort &getSlavePort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ PortID idx = InvalidPortID) override;
/* external interface */
RequestStatus makeRequest(PacketPtr pkt);
RubyPort(const Params *p);
virtual ~RubyPort() {}
- void init();
+ void init() override;
BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ PortID idx = InvalidPortID) override;
BaseSlavePort &getSlavePort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ PortID idx = InvalidPortID) override;
virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
virtual int outstandingCount() const = 0;
return m_profiler;
}
- void regStats() { m_profiler->regStats(name()); }
+ void regStats() override { m_profiler->regStats(name()); }
void collateStats() { m_profiler->collateStats(); }
- void resetStats();
+ void resetStats() override;
- void memWriteback();
+ void memWriteback() override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
void drainResume() override;
void process();
- void startup();
+ void startup() override;
bool functionalRead(Packet *ptr);
bool functionalWrite(Packet *ptr);
DrainState drain() override;
BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID);
- void init();
+ PortID idx = InvalidPortID) override;
+ void init() override;
protected:
return freqOpPoints[perf_level];
}
- void startup();
+ void startup() override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
// constructor
Process(ProcessParams *params);
- virtual void initState();
+ void initState() override;
DrainState drain() override;
void inheritFDArray(Process *p);
// override of virtual SimObject method: register statistics
- virtual void regStats();
+ void regStats() override;
// After getting registered with system object, tell process which
// system-wide context id it is assigned.
/** Schedule the timesync event at initState() when not unserializing
*/
- void initState();
+ void initState() override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
const std::string getCause() const { return cause; }
const int getCode() const { return code; }
- void process(); // process event
+ void process() override; // process event
- virtual const char *description() const;
+ const char *description() const override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
public:
CountedDrainEvent();
- void process();
+ void process() override;
void setCount(int _count) { count = _count; }
public:
CountedExitEvent(const std::string &_cause, int &_downCounter);
- void process(); // process event
+ void process() override; // process event
- virtual const char *description() const;
+ const char *description() const override;
};
SystemPort(const std::string &_name, MemObject *_owner)
: MasterPort(_name, _owner)
{ }
- bool recvTimingResp(PacketPtr pkt)
+ bool recvTimingResp(PacketPtr pkt) override
{ panic("SystemPort does not receive timing!\n"); return false; }
- void recvReqRetry()
+ void recvReqRetry() override
{ panic("SystemPort does not expect retry!\n"); }
};
* After all objects have been created and all ports are
* connected, check that the system port is connected.
*/
- virtual void init();
+ void init() override;
/**
* Get a reference to the system port that can be used by
* Additional function to return the Port of a memory object.
*/
BaseMasterPort& getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ PortID idx = InvalidPortID) override;
/** @{ */
/**
return masterIds.size();
}
- virtual void regStats();
+ void regStats() override;
/**
* Called by pseudo_inst to track the number of work items started by this
* system.
System(Params *p);
~System();
- void initState();
+ void initState() override;
const Params *params() const { return (const Params *)_params; }
using ClockedObject::unserialize;
/** Pass on regStats, serialize etc. onto Ticked */
- void regStats();
+ void regStats() override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
};
* Startup has all SrcClockDomains registered with this voltage domain, so
* try to make sure that all perf level requests from them are met.
*/
- void startup();
+ void startup() override;
/**
* Recomputes the highest (fastest, i.e., numerically lowest) requested
*/
bool sanitiseVoltages();
- void regStats();
+ void regStats() override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
projects / gem5.git / commitdiff