arm: Fix incorrect TLB permission check in aarch32

The TLB currently assumes that the pxn bit in an LPAE page descriptor
disables execution from unprivileged mode. However, according to the
architecture manual, this bit should disable execution from privileged
modes. Update the TLB implementation to reflect this behavior.

Change-Id: I7f1bb232d7a94a93fd601a9230223195ac952947
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 1bce0f7989a046c1398f03f74d4cf2b02895ac54..3fc3170481e54b025dd47f48b88003b58021da13 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013 ARM Limited
+ * Copyright (c) 2010-2013, 2016 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -720,7 +720,7 @@ TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode)
     bool xn     = te->xn || (isWritable && sctlr.wxn) ||
                             (ap == 3    && sctlr.uwxn && is_priv);
     if (is_fetch && (abt || xn ||
-                     (te->longDescFormat && te->pxn && !is_priv) ||
+                     (te->longDescFormat && te->pxn && is_priv) ||
                      (isSecure && te->ns && scr.sif))) {
         permsFaults++;
         DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d "