soc/cores/cpu/vexriscv: update submodule

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index 395c5ee2868ffbe36db290a4a4ec0eabc0f5c2b5..d7bbc2c167f1a0886c446d3c305d0ed4388570be 160000 (submodule)
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit 395c5ee2868ffbe36db290a4a4ec0eabc0f5c2b5
+Subproject commit d7bbc2c167f1a0886c446d3c305d0ed4388570be

diff --git a/litex/soc/software/include/base/csr-defs.h b/litex/soc/software/include/base/csr-defs.h
index 5f5ea84760fb35d095e0cc2794551ad40b98fc8b..d98e8dfb7b09cbbd8ba10f7a0e89bf72e60a4ab7 100644 (file)
--- a/litex/soc/software/include/base/csr-defs.h
+++ b/litex/soc/software/include/base/csr-defs.h
@@ -3,8 +3,8 @@
 
 #define CSR_MSTATUS_MIE 0x8
 
-#define CSR_IRQ_MASK 0x330
-#define CSR_IRQ_PENDING 0x360
+#define CSR_IRQ_MASK 0xBC0
+#define CSR_IRQ_PENDING 0xFC0
 
 #define CSR_DCACHE_INFO 0xCC0