add architectural note about UnVectorised

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 57b54d7f32e4b808d60d4943a81ccd4034d401ea..d47dc8fe82b7184eebcf4d4898b15ef8aef12732 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -124,6 +124,15 @@ Any operation that inherently makes no sense if repeated is termed
 which have no registers. `mtmsr` is also classed as UnVectoriseable
 because there is only one `MSR`.
 
+UnVectorised instructions are required to be detected as such if
+Prefixed (either SVP64 or SVP64Single) and an Illegal Instruction
+Trap raised.
+
+*Architectural Note: Given that a "pre-classification" Decode Phase is
+required (identifying whether the Suffix - Defined Word - is
+Arithmetic/Logical, CR-op, Load/Store or Branch-Conditional),
+adding "UnVectorised" to this phase is not unreasonable.*
+
 ## Register files, elements, and Element-width Overrides
 
 In the Upper Compliancy Levels of SVP64 the size of the GPR and FPR