*/
int set;
+ /** whether this block has been touched */
+ bool isTouched;
+
/** Number of references to this block since it was brought in. */
int refCount;
CacheBlk()
: asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
- set(-1), refCount(0)
+ set(-1), isTouched(false), refCount(0)
{}
/**
Source('fa_lru.cc')
Source('iic.cc')
Source('lru.cc')
+Source('cacheset.cc')
SimObject('iic_repl/Repl.py')
Source('iic_repl/gen.cc')
--- /dev/null
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Lisa Hsu
+ */
+
+
+#include "mem/cache/tags/cacheset.hh"
+
+CacheBlk*
+CacheSet::findBlk(Addr tag) const
+{
+ for (int i = 0; i < assoc; ++i) {
+ if (blks[i]->tag == tag && blks[i]->isValid()) {
+ return blks[i];
+ }
+ }
+ return 0;
+}
+
+void
+CacheSet::moveToHead(CacheBlk *blk)
+{
+ // nothing to do if blk is already head
+ if (blks[0] == blk)
+ return;
+
+ // write 'next' block into blks[i], moving up from MRU toward LRU
+ // until we overwrite the block we moved to head.
+
+ // start by setting up to write 'blk' into blks[0]
+ int i = 0;
+ CacheBlk *next = blk;
+
+ do {
+ assert(i < assoc);
+ // swap blks[i] and next
+ CacheBlk *tmp = blks[i];
+ blks[i] = next;
+ next = tmp;
+ ++i;
+ } while (next != blk);
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Lisa Hsu
+ */
+
+/**
+ * @file
+ * Declaration of an associative set
+ */
+
+#ifndef __CACHESET_HH__
+#define __CACHESET_HH__
+
+#include "mem/cache/blk.hh" // base class
+#include <assert.h>
+
+
+/**
+ * An associative set of cache blocks.
+ */
+class CacheSet
+{
+ public:
+ /** The associativity of this set. */
+ int assoc;
+
+ /** Cache blocks in this set, maintained in LRU order 0 = MRU. */
+ CacheBlk **blks;
+
+ /**
+ * Find a block matching the tag in this set.
+ * @param asid The address space ID.
+ * @param tag The Tag to find.
+ * @return Pointer to the block if found.
+ */
+ CacheBlk* findBlk(Addr tag) const;
+
+ /**
+ * Move the given block to the head of the list.
+ * @param blk The block to move.
+ */
+ void moveToHead(CacheBlk *blk);
+
+};
+
+#endif
#include "base/intmath.hh"
#include "mem/cache/tags/lru.hh"
#include "sim/core.hh"
+#include "cacheset.hh"
using namespace std;
-LRUBlk*
-CacheSet::findBlk(Addr tag) const
-{
- for (int i = 0; i < assoc; ++i) {
- if (blks[i]->tag == tag && blks[i]->isValid()) {
- return blks[i];
- }
- }
- return 0;
-}
-
-
-void
-CacheSet::moveToHead(LRUBlk *blk)
-{
- // nothing to do if blk is already head
- if (blks[0] == blk)
- return;
-
- // write 'next' block into blks[i], moving up from MRU toward LRU
- // until we overwrite the block we moved to head.
-
- // start by setting up to write 'blk' into blks[0]
- int i = 0;
- LRUBlk *next = blk;
-
- do {
- assert(i < assoc);
- // swap blks[i] and next
- LRUBlk *tmp = blks[i];
- blks[i] = next;
- next = tmp;
- ++i;
- } while (next != blk);
-}
-
-
// create and initialize a LRU/MRU cache structure
LRU::LRU(unsigned _numSets, unsigned _blkSize, unsigned _assoc,
unsigned _hit_latency)
warmupBound = numSets * assoc;
sets = new CacheSet[numSets];
- blks = new LRUBlk[numSets * assoc];
+ blks = new BlkType[numSets * assoc];
// allocate data storage in one big chunk
dataBlks = new uint8_t[numSets*assoc*blkSize];
for (unsigned i = 0; i < numSets; ++i) {
sets[i].assoc = assoc;
- sets[i].blks = new LRUBlk*[assoc];
+ sets[i].blks = new BlkType*[assoc];
// link in the data blocks
for (unsigned j = 0; j < assoc; ++j) {
// locate next cache block
- LRUBlk *blk = &blks[blkIndex];
+ BlkType *blk = &blks[blkIndex];
blk->data = &dataBlks[blkSize*blkIndex];
++blkIndex;
delete [] sets;
}
-LRUBlk*
+LRU::BlkType*
LRU::accessBlock(Addr addr, int &lat, int context_src)
{
Addr tag = extractTag(addr);
unsigned set = extractSet(addr);
- LRUBlk *blk = sets[set].findBlk(tag);
+ BlkType *blk = sets[set].findBlk(tag);
lat = hitLatency;
if (blk != NULL) {
// move this block to head of the MRU list
}
-LRUBlk*
+LRU::BlkType*
LRU::findBlock(Addr addr) const
{
Addr tag = extractTag(addr);
unsigned set = extractSet(addr);
- LRUBlk *blk = sets[set].findBlk(tag);
+ BlkType *blk = sets[set].findBlk(tag);
return blk;
}
-LRUBlk*
+LRU::BlkType*
LRU::findVictim(Addr addr, PacketList &writebacks)
{
unsigned set = extractSet(addr);
// grab a replacement candidate
- LRUBlk *blk = sets[set].blks[assoc-1];
+ BlkType *blk = sets[set].blks[assoc-1];
if (blk->isValid()) {
replacements[0]++;
totalRefs += blk->refCount;
}
void
-LRU::insertBlock(Addr addr, LRU::BlkType *blk, int context_src)
+LRU::insertBlock(Addr addr, BlkType *blk, int context_src)
{
if (!blk->isTouched) {
tagsInUse++;
}
void
-LRU::invalidateBlk(LRU::BlkType *blk)
+LRU::invalidateBlk(BlkType *blk)
{
if (blk) {
blk->status = 0;
#include "mem/packet.hh"
class BaseCache;
+class CacheSet;
-/**
- * LRU cache block.
- */
-class LRUBlk : public CacheBlk {
- public:
- /** Has this block been touched? Used to aid calculation of warmup time. */
- bool isTouched;
-};
-
-/**
- * An associative set of cache blocks.
- */
-class CacheSet
-{
- public:
- /** The associativity of this set. */
- int assoc;
-
- /** Cache blocks in this set, maintained in LRU order 0 = MRU. */
- LRUBlk **blks;
-
- /**
- * Find a block matching the tag in this set.
- * @param asid The address space ID.
- * @param tag The Tag to find.
- * @return Pointer to the block if found.
- */
- LRUBlk* findBlk(Addr tag) const;
-
- /**
- * Move the given block to the head of the list.
- * @param blk The block to move.
- */
- void moveToHead(LRUBlk *blk);
-};
/**
* A LRU cache tag store.
{
public:
/** Typedef the block type used in this tag store. */
- typedef LRUBlk BlkType;
+ typedef CacheBlk BlkType;
/** Typedef for a list of pointers to the local block class. */
- typedef std::list<LRUBlk*> BlkList;
+ typedef std::list<BlkType*> BlkList;
protected:
/** The number of sets in the cache. */
CacheSet *sets;
/** The cache blocks. */
- LRUBlk *blks;
+ BlkType *blks;
/** The data blocks, 1 per cache block. */
uint8_t *dataBlks;
* @param lat The access latency.
* @return Pointer to the cache block if found.
*/
- LRUBlk* accessBlock(Addr addr, int &lat, int context_src);
+ BlkType* accessBlock(Addr addr, int &lat, int context_src);
/**
* Finds the given address in the cache, do not update replacement data.
* @param asid The address space ID.
* @return Pointer to the cache block if found.
*/
- LRUBlk* findBlock(Addr addr) const;
+ BlkType* findBlock(Addr addr) const;
/**
* Find a block to evict for the address provided.
* @param writebacks List for any writebacks to be performed.
* @return The candidate block.
*/
- LRUBlk* findVictim(Addr addr, PacketList &writebacks);
+ BlkType* findVictim(Addr addr, PacketList &writebacks);
/**
* Insert the new block into the cache. For LRU this means inserting into
projects / gem5.git / commitdiff