add redirector operators for sv_freg_t to uint32 and uint64

diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 37fca6a9d2c573d37cff46d4422d2d3909eae8df..0b709979ccb6c7e5684b07842eb7f1d8d4475f1c 100644 (file)
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-MMU.store_uint32(insn.rs1(), insn.s_imm(), ((freg_t)FRS2).v[0]); // RS1
+MMU.store_uint32(insn.rs1(), insn.s_imm(), FRS2.to_uint32()); // RS1

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 3eb7a393c79e29125c5f76b80c8a9c778a2a9e56..a5d994270050fb7fb38787e020ece20fe0cf8ba0 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -885,3 +885,13 @@ void sv_proc_t::mmu_store(reg_spec_t const& spec, sv_reg_t const& offs,
     }
 }
 
+uint64_t sv_freg_t::to_uint64() const&
+{
+    return reg.v[0];
+}
+
+uint32_t sv_freg_t::to_uint32() const&
+{
+    return reg.v[0];
+}
+

diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h
index 37d6354388e9796952256adfb9fe247c0dfabe29..0fc1fb02ac95efa262c08459a225c81c432c898a 100644 (file)
--- a/riscv/sv_reg.h
+++ b/riscv/sv_reg.h
@@ -84,11 +84,14 @@ public:
     sv_freg_t(freg_t _reg, int xlen, uint8_t _elwidth) :
                 sv_regbase_t(xlen, _elwidth), reg(_reg)
                                                 {}
-
     freg_t reg;
 public:
 
   operator freg_t() const& { return reg; }
+
+  uint64_t to_uint64() const&;
+  uint32_t to_uint32() const&;
+
 };
 
 class sv_float32_t : public sv_regbase_t {