Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with

CARRY_WRAPPER in the same way since I0 and I3 could be used

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index d5106b805c77632ad57abf0314eb6d0b219d6580..f528607d6dabaa5962d9c3db807ed3fe213947c4 100644 (file)
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -83,51 +83,6 @@ static void run_ice40_opts(Module *module)
                        }
                        continue;
                }
-
-               if (cell->type == "$__ICE40_FULL_ADDER")
-               {
-                       SigSpec non_const_inputs, replacement_output;
-                       int count_zeros = 0, count_ones = 0;
-
-                       SigBit inbit[3] = {
-                               cell->getPort("\\A"),
-                               cell->getPort("\\B"),
-                               cell->getPort("\\CI")
-                       };
-                       for (int i = 0; i < 3; i++)
-                               if (inbit[i].wire == nullptr) {
-                                       if (inbit[i] == State::S1)
-                                               count_ones++;
-                                       else
-                                               count_zeros++;
-                               } else
-                                       non_const_inputs.append(inbit[i]);
-
-                       if (count_zeros >= 2)
-                               replacement_output = State::S0;
-                       else if (count_ones >= 2)
-                               replacement_output = State::S1;
-                       else if (GetSize(non_const_inputs) == 1)
-                               replacement_output = non_const_inputs;
-
-                       if (GetSize(replacement_output)) {
-                               optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
-                               module->connect(cell->getPort("\\CO")[0], replacement_output);
-                               module->design->scratchpad_set_bool("opt.did_something", true);
-                               log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
-                                               log_id(module), log_id(cell), log_signal(replacement_output));
-                               cell->type = "$lut";
-                               cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
-                               cell->setPort("\\Y", cell->getPort("\\O"));
-                               cell->unsetPort("\\B");
-                               cell->unsetPort("\\CI");
-                               cell->unsetPort("\\CO");
-                               cell->unsetPort("\\O");
-                               cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
-                               cell->setParam("\\WIDTH", 4);
-                       }
-                       continue;
-               }
        }
 
        for (auto cell : sb_lut_cells)