greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index ca8556a851f6ae82d15f0ae0ecb2d0238e2b0503..ceec2869693c1a248b0c88dc9eae92b8feb210e8 100644 (file)
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -275,15 +275,15 @@ module GP_POR(output reg RST_DONE);
        
 endmodule
 
-module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
+module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
        
        parameter PWRDN_EN = 0;
        parameter AUTO_PWRDN = 0;
-       parameter PRE_DIV = 1;
+       parameter HARDIP_DIV = 1;
        parameter FABRIC_DIV = 1;
        parameter OSC_FREQ = "25k";
        
-       initial CLKOUT_PREDIV = 0;
+       initial CLKOUT_HARDIP = 0;
        initial CLKOUT_FABRIC = 0;
        
        //output dividers not implemented for simulation
@@ -291,7 +291,7 @@ module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC)
        
        always begin
                if(PWRDN) begin
-                       CLKOUT_PREDIV = 0;
+                       CLKOUT_HARDIP = 0;
                        CLKOUT_FABRIC = 0;
                end
                else begin
@@ -306,21 +306,21 @@ module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC)
                                #250;
                        end
                        
-                       CLKOUT_PREDIV = ~CLKOUT_PREDIV;
+                       CLKOUT_HARDIP = ~CLKOUT_HARDIP;
                        CLKOUT_FABRIC = ~CLKOUT_FABRIC;
                end
        end
        
 endmodule
 
-module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
+module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
        
        parameter PWRDN_EN = 0;
        parameter AUTO_PWRDN = 0;
-       parameter PRE_DIV = 1;
+       parameter HARDIP_DIV = 1;
        parameter FABRIC_DIV = 1;
        
-       initial CLKOUT_PREDIV = 0;
+       initial CLKOUT_HARDIP = 0;
        initial CLKOUT_FABRIC = 0;
        
        //output dividers not implemented for simulation
@@ -328,13 +328,13 @@ module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRI
        
        always begin
                if(PWRDN) begin
-                       CLKOUT_PREDIV = 0;
+                       CLKOUT_HARDIP = 0;
                        CLKOUT_FABRIC = 0;
                end
                else begin
                        //half period of 27 MHz
                        #18.518;
-                       CLKOUT_PREDIV = ~CLKOUT_PREDIV;
+                       CLKOUT_HARDIP = ~CLKOUT_HARDIP;
                        CLKOUT_FABRIC = ~CLKOUT_FABRIC;
                end
        end