Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file...

--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 7595423c38cb4a912b491082b0e4655a6f7b139a..314b445e0b2d82419211b11fbd5176f787942a6f 100644 (file)
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -60,7 +60,7 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId)
     tc->setIntReg(16, cpuId);
     tc->setIntReg(0, cpuId);
 
-    AlphaFault *reset = new ResetFault;
+    AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
 
     tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect());
     tc->setNextPC(tc->readPC() + sizeof(MachInst));
@@ -176,7 +176,7 @@ AlphaISA::MiscRegFile::getDataAsid()
 }
 
 AlphaISA::MiscReg
-AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc)
+AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
 {
     uint64_t retval = 0;       // return value, default 0
 
@@ -269,12 +269,12 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc)
       case AlphaISA::IPR_DTB_IAP:
       case AlphaISA::IPR_ITB_IA:
       case AlphaISA::IPR_ITB_IAP:
-        fault = new UnimplementedOpcodeFault;
+        panic("Tried to read write only register %d\n", idx);
         break;
 
       default:
         // invalid IPR
-        fault = new UnimplementedOpcodeFault;
+        panic("Tried to read from invalid ipr %d\n", idx);
         break;
     }
 
@@ -286,13 +286,13 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc)
 int break_ipl = -1;
 #endif
 
-Fault
+void
 AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
 {
     uint64_t old;
 
     if (tc->misspeculating())
-        return NoFault;
+        return;
 
     switch (idx) {
       case AlphaISA::IPR_PALtemp0:
@@ -443,7 +443,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
       case AlphaISA::IPR_ITB_PTE_TEMP:
       case AlphaISA::IPR_DTB_PTE_TEMP:
         // read-only registers
-        return new UnimplementedOpcodeFault;
+        panic("Tried to write read only ipr %d\n", idx);
 
       case AlphaISA::IPR_HWINT_CLR:
       case AlphaISA::IPR_SL_XMIT:
@@ -547,11 +547,10 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
 
       default:
         // invalid IPR
-        return new UnimplementedOpcodeFault;
+        panic("Tried to write to invalid ipr %d\n", idx);
     }
 
     // no error...
-    return NoFault;
 }
 
 

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index f5483d9c0c260d6f14fcb03a6a3556b15eed2b69..fcf022ce1cd5e3f27c7d8d03afb1fdb1080275f3 100644 (file)
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -629,7 +629,7 @@ decode OPCODE default Unknown::unknown() {
         /* Rb is a fake dependency so here is a fun way to get
          * the parser to understand that.
          */
-                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
+                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC) + (Rb & 0);
 
 #else
                 Ra = curTick;
@@ -681,7 +681,7 @@ decode OPCODE default Unknown::unknown() {
     0x00: CallPal::call_pal({{
         if (!palValid ||
             (palPriv
-             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
+             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
             // invalid pal function code, or attempt to do privileged
             // PAL call in non-kernel mode
             fault = new UnimplementedOpcodeFault;
@@ -693,7 +693,7 @@ decode OPCODE default Unknown::unknown() {
 
             if (dopal) {
                 xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
-                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
+                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE) + palOffset;
             }
         }
     }}, IsNonSpeculative);
@@ -751,7 +751,7 @@ decode OPCODE default Unknown::unknown() {
                     miscRegIndex >= NumInternalProcRegs)
                         fault = new UnimplementedOpcodeFault;
                 else
-                    Ra = xc->readMiscRegWithEffect(miscRegIndex, fault);
+                    Ra = xc->readMiscRegWithEffect(miscRegIndex);
             }}, IsIprAccess);
         }
     }

diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index b4339a1b77a230a21eb052c6cedb2c4c0abead55..103f85775adc249c5455828b5505699931647e01 100644 (file)
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -46,7 +46,7 @@ output exec {{
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         Fault fault = NoFault; // dummy... this ipr access should not fault
-        if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR, fault))) {
+        if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR))) {
             fault = new FloatEnableFault;
         }
         return fault;

diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index 8980fcb40cc7dd953be68d1e71d0fa83e833c05f..e806adbcb614efad8b132fe977b53f52d85fbc62 100644 (file)
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -122,17 +122,16 @@ namespace AlphaISA
 
         MiscReg readReg(int misc_reg);
 
-        MiscReg readRegWithEffect(int misc_reg, Fault &fault,
-                ThreadContext *tc);
+        MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc);
 
         //These functions should be removed once the simplescalar cpu model
         //has been replaced.
         int getInstAsid();
         int getDataAsid();
 
-        Fault setReg(int misc_reg, const MiscReg &val);
+        void setReg(int misc_reg, const MiscReg &val);
 
-        Fault setRegWithEffect(int misc_reg, const MiscReg &val,
+        void setRegWithEffect(int misc_reg, const MiscReg &val,
                 ThreadContext *tc);
 
         void clear()
@@ -153,9 +152,9 @@ namespace AlphaISA
         InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
 
       private:
-        InternalProcReg readIpr(int idx, Fault &fault, ThreadContext *tc);
+        InternalProcReg readIpr(int idx, ThreadContext *tc);
 
-        Fault setIpr(int idx, InternalProcReg val, ThreadContext *tc);
+        void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
 #endif
         friend class RegFile;
     };
@@ -225,22 +224,20 @@ namespace AlphaISA
             return miscRegFile.readReg(miscReg);
         }
 
-        MiscReg readMiscRegWithEffect(int miscReg,
-                Fault &fault, ThreadContext *tc)
+        MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc)
         {
-            fault = NoFault;
-            return miscRegFile.readRegWithEffect(miscReg, fault, tc);
+            return miscRegFile.readRegWithEffect(miscReg, tc);
         }
 
-        Fault setMiscReg(int miscReg, const MiscReg &val)
+        void setMiscReg(int miscReg, const MiscReg &val)
         {
-            return miscRegFile.setReg(miscReg, val);
+            miscRegFile.setReg(miscReg, val);
         }
 
-        Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
+        void setMiscRegWithEffect(int miscReg, const MiscReg &val,
                 ThreadContext * tc)
         {
-            return miscRegFile.setRegWithEffect(miscReg, val, tc);
+            miscRegFile.setRegWithEffect(miscReg, val, tc);
         }
 
         FloatReg readFloatReg(int floatReg)
@@ -263,26 +260,24 @@ namespace AlphaISA
             return readFloatRegBits(floatReg);
         }
 
-        Fault setFloatReg(int floatReg, const FloatReg &val)
+        void setFloatReg(int floatReg, const FloatReg &val)
         {
             floatRegFile.d[floatReg] = val;
-            return NoFault;
         }
 
-        Fault setFloatReg(int floatReg, const FloatReg &val, int width)
+        void setFloatReg(int floatReg, const FloatReg &val, int width)
         {
-            return setFloatReg(floatReg, val);
+            setFloatReg(floatReg, val);
         }
 
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
+        void setFloatRegBits(int floatReg, const FloatRegBits &val)
         {
             floatRegFile.q[floatReg] = val;
-            return NoFault;
         }
 
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+        void setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
         {
-            return setFloatRegBits(floatReg, val);
+            setFloatRegBits(floatReg, val);
         }
 
         IntReg readIntReg(int intReg)
@@ -290,9 +285,9 @@ namespace AlphaISA
             return intRegFile.readReg(intReg);
         }
 
-        Fault setIntReg(int intReg, const IntReg &val)
+        void setIntReg(int intReg, const IntReg &val)
         {
-            return intRegFile.setReg(intReg, val);
+            intRegFile.setReg(intReg, val);
         }
 
         void serialize(std::ostream &os);

diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index a4527a20355f28ff81c155c6185da55e098e3fcc..368925e001645ab253c44085fdacb05f18998a29 100644 (file)
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -220,20 +220,20 @@ namespace MipsISA
             return miscRegFile[misc_reg];
         }
 
-        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ThreadContext *tc)
+        MiscReg readRegWithEffect(int misc_reg, ThreadContext *tc)
         {
             return miscRegFile[misc_reg];
         }
 
-        Fault setReg(int misc_reg, const MiscReg &val)
+        void setReg(int misc_reg, const MiscReg &val)
         {
-            miscRegFile[misc_reg] = val; return NoFault;
+            miscRegFile[misc_reg] = val;
         }
 
-        Fault setRegWithEffect(int misc_reg, const MiscReg &val,
+        void setRegWithEffect(int misc_reg, const MiscReg &val,
                                ThreadContext *tc)
         {
-            miscRegFile[misc_reg] = val; return NoFault;
+            miscRegFile[misc_reg] = val;
         }
 
         friend class RegFile;

diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 3a18c681b8e5c2b71ef23c98444adac330b7131a..dee883c4af0c2ced8f884be0c85840d2d730ec5d 100644 (file)
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -62,22 +62,20 @@ namespace MipsISA
             return miscRegFile.readReg(miscReg);
         }
 
-        MiscReg readMiscRegWithEffect(int miscReg,
-                Fault &fault, ThreadContext *tc)
+        MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc)
         {
-            fault = NoFault;
-            return miscRegFile.readRegWithEffect(miscReg, fault, tc);
+            return miscRegFile.readRegWithEffect(miscReg, tc);
         }
 
-        Fault setMiscReg(int miscReg, const MiscReg &val)
+        void setMiscReg(int miscReg, const MiscReg &val)
         {
-            return miscRegFile.setReg(miscReg, val);
+            miscRegFile.setReg(miscReg, val);
         }
 
-        Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
+        void setMiscRegWithEffect(int miscReg, const MiscReg &val,
                 ThreadContext * tc)
         {
-            return miscRegFile.setRegWithEffect(miscReg, val, tc);
+            miscRegFile.setRegWithEffect(miscReg, val, tc);
         }
 
         FloatRegVal readFloatReg(int floatReg)
@@ -100,24 +98,24 @@ namespace MipsISA
             return floatRegFile.readRegBits(floatReg,width);
         }
 
-        Fault setFloatReg(int floatReg, const FloatRegVal &val)
+        void setFloatReg(int floatReg, const FloatRegVal &val)
         {
-            return floatRegFile.setReg(floatReg, val, SingleWidth);
+            floatRegFile.setReg(floatReg, val, SingleWidth);
         }
 
-        Fault setFloatReg(int floatReg, const FloatRegVal &val, int width)
+        void setFloatReg(int floatReg, const FloatRegVal &val, int width)
         {
-            return floatRegFile.setReg(floatReg, val, width);
+            floatRegFile.setReg(floatReg, val, width);
         }
 
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val)
+        void setFloatRegBits(int floatReg, const FloatRegBits &val)
         {
-            return floatRegFile.setRegBits(floatReg, val, SingleWidth);
+            floatRegFile.setRegBits(floatReg, val, SingleWidth);
         }
 
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+        void setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
         {
-            return floatRegFile.setRegBits(floatReg, val, width);
+            floatRegFile.setRegBits(floatReg, val, width);
         }
 
         IntReg readIntReg(int intReg)
@@ -125,9 +123,9 @@ namespace MipsISA
             return intRegFile.readReg(intReg);
         }
 
-        Fault setIntReg(int intReg, const IntReg &val)
+        void setIntReg(int intReg, const IntReg &val)
         {
-            return intRegFile.setReg(intReg, val);
+            intRegFile.setReg(intReg, val);
         }
       protected:
 

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index a64ff09bb8261af6375ac78cdbf2d3cd7e3ec975..a5f43367d7b8436d4980beace9328d443791b509 100644 (file)
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -353,14 +353,14 @@ decode OP default Unknown::unknown()
                     0x1: Nop::membar({{/*stuff*/}});
                 }
                 default: rdasr({{
-                Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
+                Rd = xc->readMiscRegWithEffect(RS1 + AsrStart);
                 }});
             }
             0x29: HPriv::rdhpr({{
-                Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
+                Rd = xc->readMiscRegWithEffect(RS1 + HprStart);
             }});
             0x2A: Priv::rdpr({{
-                Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
+                Rd = xc->readMiscRegWithEffect(RS1 + PrStart);
             }});
             0x2B: BasicOperate::flushw({{
                 if(NWindows - 2 - Cansave == 0)

diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index bf4572878f1f4ee8aac6f04dad10cd564ca212e0..2f3cfb4174004ab3e218ab430976e94ab91fa6c6 100644 (file)
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -59,20 +59,21 @@ string SparcISA::getMiscRegName(RegIndex index)
 
 //XXX These need an implementation someplace
 /** Fullsystem only register version of ReadRegWithEffect() */
-MiscReg MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
+MiscReg MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext *tc);
 /** Fullsystem only register version of SetRegWithEffect() */
-Fault MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
+void MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         ThreadContext * tc);
 #endif
 
 void MiscRegFile::reset()
 {
-    pstateFields.pef = 0; //No FPU
+    //pstateFields.pef = 0; //No FPU
     //pstateFields.pef = 1; //FPU
 #if FULL_SYSTEM
     //For SPARC, when a system is first started, there is a power
     //on reset Trap which sets the processor into the following state.
     //Bits that aren't set aren't defined on startup.
+    //XXX this code should be moved into the POR fault.
     tl = MaxTL;
     gl = MaxGL;
 
@@ -98,22 +99,6 @@ void MiscRegFile::reset()
     hintp = 0; // no interrupts pending
     hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
     hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
-#else
-/*         //This sets up the initial state of the processor for usermode processes
-    pstateFields.priv = 0; //Process runs in user mode
-    pstateFields.ie = 1; //Interrupts are enabled
-    fsrFields.rd = 0; //Round to nearest
-    fsrFields.tem = 0; //Floating point traps not enabled
-    fsrFields.ns = 0; //Non standard mode off
-    fsrFields.qne = 0; //Floating point queue is empty
-    fsrFields.aexc = 0; //No accrued exceptions
-    fsrFields.cexc = 0; //No current exceptions
-
-    //Register window management registers
-    otherwin = 0; //No windows contain info from other programs
-    canrestore = 0; //There are no windows to pop
-    cansave = MaxTL - 2; //All windows are available to save into
-    cleanwin = MaxTL;*/
 #endif
 }
 
@@ -337,6 +322,30 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
     }
 }
 
+inline void MiscRegFile::setImplicitAsis()
+{
+    //The spec seems to use trap level to indicate the privilege level of the
+    //processor. It's unclear whether the implicit ASIs should directly depend
+    //on the trap level, or if they should really be based on the privelege
+    //bits
+    if(tl == 0)
+    {
+        implicitInstAsi = implicitDataAsi =
+            pstateFields.cle ? ASI_PRIMARY_LITTLE : ASI_PRIMARY;
+    }
+    else if(tl <= MaxPTL)
+    {
+        implicitInstAsi = ASI_NUCLEUS;
+        implicitDataAsi = pstateFields.cle ? ASI_NUCLEUS_LITTLE : ASI_NUCLEUS;
+    }
+    else
+    {
+        //This is supposed to force physical addresses to match the spec.
+        //It might not because of context values and partition values.
+        implicitInstAsi = implicitDataAsi = ASI_REAL;
+    }
+}
+
 void MiscRegFile::setRegWithEffect(int miscReg,
         const MiscReg &val, ThreadContext * tc)
 {
@@ -352,6 +361,14 @@ void MiscRegFile::setRegWithEffect(int miscReg,
         case MISCREG_PCR:
           //Set up performance counting based on pcr value
           break;
+        case MISCREG_PSTATE:
+          pstate = val;
+          setImplicitAsis();
+          return;
+        case MISCREG_TL:
+          tl = val;
+          setImplicitAsis();
+          return;
         case MISCREG_CWP:
           tc->changeRegFileContext(CONTEXT_CWP, val);
           break;
@@ -389,6 +406,8 @@ void MiscRegFile::serialize(std::ostream & os)
     SERIALIZE_ARRAY(htstate, MaxTL);
     SERIALIZE_SCALAR(htba);
     SERIALIZE_SCALAR(hstick_cmpr);
+    SERIALIZE_SCALAR((int)implicitInstAsi);
+    SERIALIZE_SCALAR((int)implicitDataAsi);
 }
 
 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
@@ -418,5 +437,10 @@ void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
     UNSERIALIZE_ARRAY(htstate, MaxTL);
     UNSERIALIZE_SCALAR(htba);
     UNSERIALIZE_SCALAR(hstick_cmpr);
+    int temp;
+    UNSERIALIZE_SCALAR(temp);
+    implicitInstAsi = (ASI)temp;
+    UNSERIALIZE_SCALAR(temp);
+    implicitDataAsi = (ASI)temp;
 }
 

diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index 771cb1ed680fe76802db3bf65e6cd0894f7e7118..ac1ad90b9956987d0e6b6c6a0c17c1ffea8962d8 100644 (file)
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -32,9 +32,11 @@
 #ifndef __ARCH_SPARC_MISCREGFILE_HH__
 #define __ARCH_SPARC_MISCREGFILE_HH__
 
+#include "arch/sparc/asi.hh"
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/types.hh"
+#include "cpu/cpuevent.hh"
 
 #include <string>
 
@@ -329,6 +331,9 @@ namespace SparcISA
             } fsrFields;
         };
 
+        ASI implicitInstAsi;
+        ASI implicitDataAsi;
+
         // These need to check the int_dis field and if 0 then
         // set appropriate bit in softint and checkinterrutps on the cpu
 #if FULL_SYSTEM
@@ -374,6 +379,16 @@ namespace SparcISA
         void setRegWithEffect(int miscReg,
                 const MiscReg &val, ThreadContext * tc);
 
+        ASI getInstAsid()
+        {
+            return implicitInstAsi;
+        }
+
+        ASI getDataAsid()
+        {
+            return implicitDataAsi;
+        }
+
         void serialize(std::ostream & os);
 
         void unserialize(Checkpoint * cp, const std::string & section);
@@ -385,6 +400,7 @@ namespace SparcISA
         bool isHyperPriv() { return hpstateFields.hpriv; }
         bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
         bool isNonPriv() { return !isPriv(); }
+        inline void setImplicitAsis();
     };
 }
 

diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
index 5eb874d395efdac9f7315e20103591f54c572474..65e6017dafb441255316fe33480bc0521bf6b5f5 100644 (file)
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -79,24 +79,20 @@ MiscReg RegFile::readMiscReg(int miscReg)
     return miscRegFile.readReg(miscReg);
 }
 
-MiscReg RegFile::readMiscRegWithEffect(int miscReg,
-        Fault &fault, ThreadContext *tc)
+MiscReg RegFile::readMiscRegWithEffect(int miscReg, ThreadContext *tc)
 {
-    fault = NoFault;
     return miscRegFile.readRegWithEffect(miscReg, tc);
 }
 
-Fault RegFile::setMiscReg(int miscReg, const MiscReg &val)
+void RegFile::setMiscReg(int miscReg, const MiscReg &val)
 {
     miscRegFile.setReg(miscReg, val);
-    return NoFault;
 }
 
-Fault RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
+void RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
         ThreadContext * tc)
 {
     miscRegFile.setRegWithEffect(miscReg, val, tc);
-    return NoFault;
 }
 
 FloatReg RegFile::readFloatReg(int floatReg, int width)
@@ -122,27 +118,26 @@ FloatRegBits RegFile::readFloatRegBits(int floatReg)
             FloatRegFile::SingleWidth);
 }
 
-Fault RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
+void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
 {
-    return floatRegFile.setReg(floatReg, val, width);
+    floatRegFile.setReg(floatReg, val, width);
 }
 
-Fault RegFile::setFloatReg(int floatReg, const FloatReg &val)
+void RegFile::setFloatReg(int floatReg, const FloatReg &val)
 {
     //Use the "natural" width of a single float
-    return setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
+    setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
 }
 
-Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
 {
-    return floatRegFile.setRegBits(floatReg, val, width);
+    floatRegFile.setRegBits(floatReg, val, width);
 }
 
-Fault RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
+void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
 {
     //Use the "natural" width of a single float
-    return floatRegFile.setRegBits(floatReg, val,
-            FloatRegFile::SingleWidth);
+    floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth);
 }
 
 IntReg RegFile::readIntReg(int intReg)
@@ -150,9 +145,9 @@ IntReg RegFile::readIntReg(int intReg)
     return intRegFile.readReg(intReg);
 }
 
-Fault RegFile::setIntReg(int intReg, const IntReg &val)
+void RegFile::setIntReg(int intReg, const IntReg &val)
 {
-    return intRegFile.setReg(intReg, val);
+    intRegFile.setReg(intReg, val);
 }
 
 void RegFile::serialize(std::ostream &os)

diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index 500fbbba4dd362dbeb69778e0a3dd4877ab7770f..9f33435f69e8c30fba71f8259864d18fbfa2adaa 100644 (file)
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -32,7 +32,6 @@
 #ifndef __ARCH_SPARC_REGFILE_HH__
 #define __ARCH_SPARC_REGFILE_HH__
 
-#include "arch/sparc/faults.hh"
 #include "arch/sparc/floatregfile.hh"
 #include "arch/sparc/intregfile.hh"
 #include "arch/sparc/isa_traits.hh"
@@ -76,14 +75,23 @@ namespace SparcISA
 
         MiscReg readMiscReg(int miscReg);
 
-        MiscReg readMiscRegWithEffect(int miscReg,
-                Fault &fault, ThreadContext *tc);
+        MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc);
 
-        Fault setMiscReg(int miscReg, const MiscReg &val);
+        void setMiscReg(int miscReg, const MiscReg &val);
 
-        Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
+        void setMiscRegWithEffect(int miscReg, const MiscReg &val,
                 ThreadContext * tc);
 
+        ASI instAsid()
+        {
+            return miscRegFile.getInstAsid();
+        }
+
+        ASI dataAsid()
+        {
+            return miscRegFile.getDataAsid();
+        }
+
         FloatReg readFloatReg(int floatReg, int width);
 
         FloatReg readFloatReg(int floatReg);
@@ -92,17 +100,17 @@ namespace SparcISA
 
         FloatRegBits readFloatRegBits(int floatReg);
 
-        Fault setFloatReg(int floatReg, const FloatReg &val, int width);
+        void setFloatReg(int floatReg, const FloatReg &val, int width);
 
-        Fault setFloatReg(int floatReg, const FloatReg &val);
+        void setFloatReg(int floatReg, const FloatReg &val);
 
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
+        void setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
 
-        Fault setFloatRegBits(int floatReg, const FloatRegBits &val);
+        void setFloatRegBits(int floatReg, const FloatRegBits &val);
 
         IntReg readIntReg(int intReg);
 
-        Fault setIntReg(int intReg, const IntReg &val);
+        void setIntReg(int intReg, const IntReg &val);
 
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 35ff08b430890f9f13cc9741c3ac7af4443eb7ea..0d42e2c97acb842904b0c605016f26c2fe4cd0d7 100644 (file)
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -31,5 +31,33 @@
 #ifndef __ARCH_SPARC_TLB_HH__
 #define __ARCH_SPARC_TLB_HH__
 
+#include "sim/faults.hh"
+
+class ThreadContext;
+
+namespace SparcISA
+{
+    class TLB
+    {
+    };
+
+    class ITB : public TLB
+    {
+      public:
+        Fault translate(RequestPtr &req, ThreadContext *tc) const
+        {
+            return NoFault;
+        }
+    };
+
+    class DTB : public TLB
+    {
+      public:
+        Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const
+        {
+            return NoFault;
+        }
+    };
+}
 
 #endif // __ARCH_SPARC_TLB_HH__

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 7c01bdc39e9a86770cde5c8b89078ccb5144cfaf..0df0147ae30c5e1b02d70b9c3c82f852c4f5205a 100644 (file)
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -47,9 +47,12 @@
 
 // forward declarations
 #if FULL_SYSTEM
+namespace TheISA
+{
+    class ITB;
+    class DTB;
+}
 class Processor;
-class AlphaITB;
-class AlphaDTB;
 class PhysicalMemory;
 
 class RemoteGDB;
@@ -96,8 +99,8 @@ class CheckerCPU : public BaseCPU
     struct Params : public BaseCPU::Params
     {
 #if FULL_SYSTEM
-        AlphaITB *itb;
-        AlphaDTB *dtb;
+        TheISA::ITB *itb;
+        TheISA::DTB *dtb;
 #else
         Process *process;
 #endif
@@ -140,8 +143,8 @@ class CheckerCPU : public BaseCPU
 
     ThreadContext *tc;
 
-    AlphaITB *itb;
-    AlphaDTB *dtb;
+    TheISA::ITB *itb;
+    TheISA::DTB *dtb;
 
 #if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
@@ -301,19 +304,19 @@ class CheckerCPU : public BaseCPU
         return thread->readMiscReg(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+    MiscReg readMiscRegWithEffect(int misc_reg)
     {
-        return thread->readMiscRegWithEffect(misc_reg, fault);
+        return thread->readMiscRegWithEffect(misc_reg);
     }
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
         result.integer = val;
         miscRegIdxs.push(misc_reg);
         return thread->setMiscReg(misc_reg, val);
     }
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
         miscRegIdxs.push(misc_reg);
         return thread->setMiscRegWithEffect(misc_reg, val);

diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index b2806d40b9b55da5e01e8dfe020fca7b999fc2fd..cd399dd222886b70cfae11101d8bdcdb7cb86c34 100644 (file)
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -87,9 +87,9 @@ class CheckerThreadContext : public ThreadContext
 
     PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
 
-    AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
+    TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
 
-    AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
+    TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
 
     Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
 
@@ -248,19 +248,19 @@ class CheckerThreadContext : public ThreadContext
     MiscReg readMiscReg(int misc_reg)
     { return actualTC->readMiscReg(misc_reg); }
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
-    { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
+    MiscReg readMiscRegWithEffect(int misc_reg)
+    { return actualTC->readMiscRegWithEffect(misc_reg); }
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
         checkerTC->setMiscReg(misc_reg, val);
-        return actualTC->setMiscReg(misc_reg, val);
+        actualTC->setMiscReg(misc_reg, val);
     }
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
         checkerTC->setMiscRegWithEffect(misc_reg, val);
-        return actualTC->setMiscRegWithEffect(misc_reg, val);
+        actualTC->setMiscRegWithEffect(misc_reg, val);
     }
 
     unsigned readStCondFailures()

diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index e28b33193aac721df394ab2455cd7ce1fd10bffb..13f70fa794d01513e9fa520ad0a9d805225b71dc 100644 (file)
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -101,14 +101,14 @@ class ExecContext {
 
     /** Reads a miscellaneous register, handling any architectural
      * side effects due to reading that register. */
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
+    MiscReg readMiscRegWithEffect(int misc_reg);
 
     /** Sets a miscellaneous register. */
-    Fault setMiscReg(int misc_reg, const MiscReg &val);
+    void setMiscReg(int misc_reg, const MiscReg &val);
 
     /** Sets a miscellaneous register, handling any architectural
      * side effects due to writing that register. */
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
 
     /** Records the effective address of the instruction.  Only valid
      * for memory ops. */

diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh
index 474fce02a3fc023874c659f2fd7aca1a09db05f5..01749a2a29822646446d0c26220af7d68784d4e9 100644 (file)
--- a/src/cpu/o3/alpha/cpu.hh
+++ b/src/cpu/o3/alpha/cpu.hh
@@ -37,6 +37,12 @@
 #include "cpu/o3/cpu.hh"
 #include "sim/byteswap.hh"
 
+namespace TheISA
+{
+    class ITB;
+    class DTB;
+}
+
 class EndQuiesceEvent;
 namespace Kernel {
     class Statistics;
@@ -73,9 +79,9 @@ class AlphaO3CPU : public FullO3CPU<Impl>
 
 #if FULL_SYSTEM
     /** ITB pointer. */
-    AlphaITB *itb;
+    AlphaISA::ITB *itb;
     /** DTB pointer. */
-    AlphaDTB *dtb;
+    AlphaISA::DTB *dtb;
 #endif
 
     /** Registers statistics. */
@@ -126,15 +132,15 @@ class AlphaO3CPU : public FullO3CPU<Impl>
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
      */
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid);
+    MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
 
     /** Sets a miscellaneous register. */
-    Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
+    void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
 
     /** Initiates a squash of all in-flight instructions for a given
      * thread.  The source of the squash is an external update of

diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index ff123a6f7b2e2e5b118f71b04869d70c73c17a68..a00dd500547b8263931086257579e4d4a92de462 100644 (file)
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -54,8 +54,8 @@ Param<int> activity;
 #if FULL_SYSTEM
 SimObjectParam<System *> system;
 Param<int> cpu_id;
-SimObjectParam<AlphaITB *> itb;
-SimObjectParam<AlphaDTB *> dtb;
+SimObjectParam<AlphaISA::ITB *> itb;
+SimObjectParam<AlphaISA::DTB *> dtb;
 Param<Tick> profile;
 #else
 SimObjectVectorParam<Process *> workload;

diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index a57c5d9ed713968fc3956b73825e4cc8e92b0dc5..7f10e43c2aefe845202b901f4fc3994d296986db 100644 (file)
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -198,25 +198,24 @@ AlphaO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
 
 template <class Impl>
 TheISA::MiscReg
-AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault,
-                                        unsigned tid)
+AlphaO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid);
+    return this->regFile.readMiscRegWithEffect(misc_reg, tid);
 }
 
 template <class Impl>
-Fault
+void
 AlphaO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
 {
-    return this->regFile.setMiscReg(misc_reg, val, tid);
+    this->regFile.setMiscReg(misc_reg, val, tid);
 }
 
 template <class Impl>
-Fault
+void
 AlphaO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
                                        unsigned tid)
 {
-    return this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
+    this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
 }
 
 template <class Impl>

diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 31a6f7753e4659fa07308487e2472f506c3000f5..e711de510396cc43df4528b6780174963c03e937 100644 (file)
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -102,14 +102,13 @@ class AlphaDynInst : public BaseDynInst<Impl>
     /** Reads a misc. register, including any side-effects the read
      * might have as defined by the architecture.
      */
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+    MiscReg readMiscRegWithEffect(int misc_reg)
     {
-        return this->cpu->readMiscRegWithEffect(misc_reg, fault,
-                                                this->threadNumber);
+        return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
     }
 
     /** Sets a misc. register. */
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
         this->instResult.integer = val;
         return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
@@ -118,7 +117,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
     /** Sets a misc. register, including any side-effects the write
      * might have as defined by the architecture.
      */
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
         return this->cpu->setMiscRegWithEffect(misc_reg, val,
                                                this->threadNumber);

diff --git a/src/cpu/o3/alpha/params.hh b/src/cpu/o3/alpha/params.hh
index c618cee08bed5a309cdaeefe7a04e15364387fad..b6b84b2a132faaa19f594cb35e78e3ab50010e25 100644 (file)
--- a/src/cpu/o3/alpha/params.hh
+++ b/src/cpu/o3/alpha/params.hh
@@ -35,8 +35,11 @@
 #include "cpu/o3/params.hh"
 
 //Forward declarations
-class AlphaDTB;
-class AlphaITB;
+namespace AlphaISA
+{
+    class DTB;
+    class ITB;
+}
 class MemObject;
 class Process;
 class System;
@@ -52,8 +55,8 @@ class AlphaSimpleParams : public O3Params
   public:
 
 #if FULL_SYSTEM
-    AlphaITB *itb;
-    AlphaDTB *dtb;
+    AlphaISA::ITB *itb;
+    AlphaISA::DTB *dtb;
 #endif
 };
 

diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh
index 70a09940f3d9fb676527c313c3029a3a599474d4..f0cecee35a278d49cfa53465eb4149da02750707 100644 (file)
--- a/src/cpu/o3/alpha/thread_context.hh
+++ b/src/cpu/o3/alpha/thread_context.hh
@@ -37,10 +37,10 @@ class AlphaTC : public O3ThreadContext<Impl>
   public:
 #if FULL_SYSTEM
     /** Returns a pointer to the ITB. */
-    virtual AlphaITB *getITBPtr() { return this->cpu->itb; }
+    virtual AlphaISA::ITB *getITBPtr() { return this->cpu->itb; }
 
     /** Returns a pointer to the DTB. */
-    virtual AlphaDTB *getDTBPtr() { return this->cpu->dtb; }
+    virtual AlphaISA::DTB *getDTBPtr() { return this->cpu->dtb; }
 
     /** Returns pointer to the quiesce event. */
     virtual EndQuiesceEvent *getQuiesceEvent()

diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
index 02c8174993b4f3a744123d5b640ec97edd9a4eae..8b028e3a0db145d709527bbdad39004389464f8e 100644 (file)
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -67,8 +67,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
     Param<Tick> progress_interval;
 
 #if FULL_SYSTEM
-    SimObjectParam<AlphaITB *> itb;
-    SimObjectParam<AlphaDTB *> dtb;
+    SimObjectParam<TheISA::ITB *> itb;
+    SimObjectParam<TheISA::DTB *> dtb;
     SimObjectParam<System *> system;
     Param<int> cpu_id;
     Param<Tick> profile;

diff --git a/src/cpu/o3/mips/cpu.hh b/src/cpu/o3/mips/cpu.hh
index bf04b9f69e3d8d6eaf85c250c9526872f55ba610..7e6268cdfbcbce7ad9efd4ed6bd6dba8ab947bc0 100755 (executable)
--- a/src/cpu/o3/mips/cpu.hh
+++ b/src/cpu/o3/mips/cpu.hh
@@ -92,16 +92,15 @@ class MipsO3CPU : public FullO3CPU<Impl>
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
      */
-    TheISA::MiscReg readMiscRegWithEffect(int misc_reg,
-            Fault &fault, unsigned tid);
+    TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
 
     /** Sets a miscellaneous register. */
-    Fault setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
+    void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
 
     /** Sets a misc. register, including any side effects the write
      * might have as defined by the architecture.
      */
-    Fault setMiscRegWithEffect(int misc_reg,
+    void setMiscRegWithEffect(int misc_reg,
             const TheISA::MiscReg &val, unsigned tid);
 
     /** Initiates a squash of all in-flight instructions for a given

diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh
index e087416264afafa739a611ea3229466b55ae21b4..5633acee154c81cbb5d1da2f0a162002f2a9fb63 100644 (file)
--- a/src/cpu/o3/mips/cpu_impl.hh
+++ b/src/cpu/o3/mips/cpu_impl.hh
@@ -156,25 +156,24 @@ MipsO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
 
 template <class Impl>
 MiscReg
-MipsO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault,
-                                        unsigned tid)
+MipsO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
 {
-    return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid);
+    return this->regFile.readMiscRegWithEffect(misc_reg, tid);
 }
 
 template <class Impl>
-Fault
+void
 MipsO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
 {
-    return this->regFile.setMiscReg(misc_reg, val, tid);
+    this->regFile.setMiscReg(misc_reg, val, tid);
 }
 
 template <class Impl>
-Fault
+void
 MipsO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
                                        unsigned tid)
 {
-    return this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
+    this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
 }
 
 template <class Impl>

diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index aa30bfa1e214eaccfed55bd774e38c6f9e41bdff..9e95b2bfba57c8d08d8427e94ca5d5262f0a7859 100755 (executable)
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -103,23 +103,22 @@ class MipsDynInst : public BaseDynInst<Impl>
     /** Reads a misc. register, including any side-effects the read
      * might have as defined by the architecture.
      */
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+    MiscReg readMiscRegWithEffect(int misc_reg)
     {
-        return this->cpu->readMiscRegWithEffect(misc_reg, fault,
-                                                this->threadNumber);
+        return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
     }
 
     /** Sets a misc. register. */
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
         this->instResult.integer = val;
-        return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
+        this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
     }
 
     /** Sets a misc. register, including any side-effects the write
      * might have as defined by the architecture.
      */
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
         return this->cpu->setMiscRegWithEffect(misc_reg, val,
                                                this->threadNumber);

diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 10f6db390fa70a2d402261b0d980f2eadc183035..29ee19e49c2bf5a29708cc70a65805580e7cf85a 100644 (file)
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -37,7 +37,6 @@
 #include "base/trace.hh"
 #include "config/full_system.hh"
 #include "cpu/o3/comm.hh"
-#include "sim/faults.hh"
 
 #if FULL_SYSTEM
 #include "kern/kernel_stats.hh"
@@ -232,22 +231,21 @@ class PhysRegFile
         return miscRegs[thread_id].readReg(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault,
-                                  unsigned thread_id)
+    MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id)
     {
-        return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
+        return miscRegs[thread_id].readRegWithEffect(misc_reg,
                                                      cpu->tcBase(thread_id));
     }
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
+    void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
     {
-        return miscRegs[thread_id].setReg(misc_reg, val);
+        miscRegs[thread_id].setReg(misc_reg, val);
     }
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val,
                                unsigned thread_id)
     {
-        return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
+        miscRegs[thread_id].setRegWithEffect(misc_reg, val,
                                                     cpu->tcBase(thread_id));
     }
 

diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 9ca02b9f3efef727467d838251d01bd040205deb..4556c5e2277e4badea36b45d3a8105de1f713cde 100755 (executable)
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -201,15 +201,15 @@ class O3ThreadContext : public ThreadContext
 
     /** Reads a misc. register, including any side-effects the
      * read might have as defined by the architecture. */
-    virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
-    { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->readTid()); }
+    virtual MiscReg readMiscRegWithEffect(int misc_reg)
+    { return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); }
 
     /** Sets a misc. register. */
-    virtual Fault setMiscReg(int misc_reg, const MiscReg &val);
+    virtual void setMiscReg(int misc_reg, const MiscReg &val);
 
     /** Sets a misc. register, including any side-effects the
      * write might have as defined by the architecture. */
-    virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+    virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
 
     /** Returns the number of consecutive store conditional failures. */
     // @todo: Figure out where these store cond failures should go.

diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 2bc194d534b8ec9fc330fff9887f1c1659e43e4c..81750ada76ee7f84f9e566357bcf04bad04983bf 100755 (executable)
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -439,33 +439,28 @@ O3ThreadContext<Impl>::setNextPC(uint64_t val)
 }
 
 template <class Impl>
-Fault
+void
 O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
 {
-    Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid());
+    cpu->setMiscReg(misc_reg, val, thread->readTid());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
         cpu->squashFromTC(thread->readTid());
     }
-
-    return ret_fault;
 }
 
 template <class Impl>
-Fault
+void
 O3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg,
                                                 const MiscReg &val)
 {
-    Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val,
-                                                thread->readTid());
+    cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid());
 
     // Squash if we're not already in a state update mode.
     if (!thread->trapPending && !thread->inSyscall) {
         cpu->squashFromTC(thread->readTid());
     }
-
-    return ret_fault;
 }
 
 #if !FULL_SYSTEM

diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc
index b4c4686b74ccce633c1da037c19129b0d98bc732..9ad1e639f1f67ab60c4e509d6aa651b9492b7e78 100644 (file)
--- a/src/cpu/ozone/checker_builder.cc
+++ b/src/cpu/ozone/checker_builder.cc
@@ -68,8 +68,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
     Param<Tick> progress_interval;
 
 #if FULL_SYSTEM
-    SimObjectParam<AlphaITB *> itb;
-    SimObjectParam<AlphaDTB *> dtb;
+    SimObjectParam<TheISA::ITB *> itb;
+    SimObjectParam<TheISA::DTB *> dtb;
     SimObjectParam<System *> system;
     Param<int> cpu_id;
     Param<Tick> profile;

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index bd46b198bfc3e43c894a5fc4e94a1bb297a22599..14c32620bc3ffe832185874defa857c88cc1ea8a 100644 (file)
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -51,8 +51,11 @@
 #if FULL_SYSTEM
 #include "arch/alpha/tlb.hh"
 
-class AlphaITB;
-class AlphaDTB;
+namespace TheISA
+{
+    class ITB;
+    class DTB;
+}
 class PhysicalMemory;
 class MemoryController;
 
@@ -120,9 +123,9 @@ class OzoneCPU : public BaseCPU
 
         PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
 
-        AlphaITB *getITBPtr() { return cpu->itb; }
+        TheISA::ITB *getITBPtr() { return cpu->itb; }
 
-        AlphaDTB * getDTBPtr() { return cpu->dtb; }
+        TheISA::DTB * getDTBPtr() { return cpu->dtb; }
 
         Kernel::Statistics *getKernelStats()
         { return thread->getKernelStats(); }
@@ -224,11 +227,11 @@ class OzoneCPU : public BaseCPU
         // ISA stuff:
         MiscReg readMiscReg(int misc_reg);
 
-        MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
+        MiscReg readMiscRegWithEffect(int misc_reg);
 
-        Fault setMiscReg(int misc_reg, const MiscReg &val);
+        void setMiscReg(int misc_reg, const MiscReg &val);
 
-        Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+        void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
 
         unsigned readStCondFailures()
         { return thread->storeCondFailures; }

diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index 730158258f2f8bf82c0fd330fa7efaf5fc6056b4..8a572ba38ca2646ab54fa8eee22d73498b38b64d 100644 (file)
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -61,8 +61,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
 #if FULL_SYSTEM
 SimObjectParam<System *> system;
 Param<int> cpu_id;
-SimObjectParam<AlphaITB *> itb;
-SimObjectParam<AlphaDTB *> dtb;
+SimObjectParam<TheISA::ITB *> itb;
+SimObjectParam<TheISA::DTB *> dtb;
 Param<Tick> profile;
 #else
 SimObjectVectorParam<Process *> workload;

diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index bf547bf943325770ccd49331cb70eb1bbb8d76f4..b34b061d954f3bf618686edbf02acdd43a17f6d2 100644 (file)
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -1156,37 +1156,31 @@ OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
 
 template <class Impl>
 TheISA::MiscReg
-OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg, Fault &fault)
+OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg)
 {
-    return thread->miscRegFile.readRegWithEffect(misc_reg,
-                                                 fault, this);
+    return thread->miscRegFile.readRegWithEffect(misc_reg, this);
 }
 
 template <class Impl>
-Fault
+void
 OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
 {
     // Needs to setup a squash event unless we're in syscall mode
-    Fault ret_fault = thread->miscRegFile.setReg(misc_reg, val);
+    thread->miscRegFile.setReg(misc_reg, val);
 
     if (!thread->inSyscall) {
         cpu->squashFromTC();
     }
-
-    return ret_fault;
 }
 
 template <class Impl>
-Fault
+void
 OzoneCPU<Impl>::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 {
     // Needs to setup a squash event unless we're in syscall mode
-    Fault ret_fault = thread->miscRegFile.setRegWithEffect(misc_reg, val,
-                                                           this);
+    thread->miscRegFile.setRegWithEffect(misc_reg, val, this);
 
     if (!thread->inSyscall) {
         cpu->squashFromTC();
     }
-
-    return ret_fault;
 }

diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index d3871568a3771b8172f27aba5966861c39830179..532317b083ffcf764fb24f1be50b6ac5d71e684f 100644 (file)
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -230,11 +230,11 @@ class OzoneDynInst : public BaseDynInst<Impl>
     // ISA stuff
     MiscReg readMiscReg(int misc_reg);
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
+    MiscReg readMiscRegWithEffect(int misc_reg);
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val);
+    void setMiscReg(int misc_reg, const MiscReg &val);
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
 
 #if FULL_SYSTEM
     Fault hwrei();

diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index d86f2dc8b36f716b6599faf9dde68c72feabb791..68736ae61108a5d4d33bd7eac054281401a6b893 100644 (file)
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -223,24 +223,24 @@ OzoneDynInst<Impl>::readMiscReg(int misc_reg)
 
 template <class Impl>
 TheISA::MiscReg
-OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault)
+OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg)
 {
-    return this->thread->readMiscRegWithEffect(misc_reg, fault);
+    return this->thread->readMiscRegWithEffect(misc_reg);
 }
 
 template <class Impl>
-Fault
+void
 OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
 {
     this->setIntResult(val);
-    return this->thread->setMiscReg(misc_reg, val);
+    this->thread->setMiscReg(misc_reg, val);
 }
 
 template <class Impl>
-Fault
+void
 OzoneDynInst<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 {
-    return this->thread->setMiscRegWithEffect(misc_reg, val);
+    this->thread->setMiscRegWithEffect(misc_reg, val);
 }
 
 #if FULL_SYSTEM

diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc
index baaf7c70844ce4e56b08b9b5f4936b0936a9d385..e7214d2ba911a611499032d07659799d1faae2fa 100644 (file)
--- a/src/cpu/ozone/simple_cpu_builder.cc
+++ b/src/cpu/ozone/simple_cpu_builder.cc
@@ -64,8 +64,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
 #if FULL_SYSTEM
 SimObjectParam<System *> system;
 Param<int> cpu_id;
-SimObjectParam<AlphaITB *> itb;
-SimObjectParam<AlphaDTB *> dtb;
+SimObjectParam<TheISA::ITB *> itb;
+SimObjectParam<TheISA::DTB *> dtb;
 #else
 SimObjectVectorParam<Process *> workload;
 //SimObjectParam<PageTable *> page_table;

diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh
index 3f63d2e1dc4014427abe8ca1bbd9ad2e91712dc5..3473b088cc41e9bfe8300bcb45400bcfdce3c72a 100644 (file)
--- a/src/cpu/ozone/simple_params.hh
+++ b/src/cpu/ozone/simple_params.hh
@@ -34,8 +34,11 @@
 #include "cpu/ozone/cpu.hh"
 
 //Forward declarations
-class AlphaDTB;
-class AlphaITB;
+namespace TheISA
+{
+    class DTB;
+    class ITB;
+}
 class FUPool;
 class MemObject;
 class PageTable;
@@ -53,7 +56,7 @@ class SimpleParams : public BaseCPU::Params
   public:
 
 #if FULL_SYSTEM
-    AlphaITB *itb; AlphaDTB *dtb;
+    TheISA::ITB *itb; TheISA::DTB *dtb;
 #else
     std::vector<Process *> workload;
 #endif // FULL_SYSTEM

diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index 985e09b5273fe1967a9565602a5d2a3f00c60d72..ec51251b765bdd44c0ce15a0ca447060907ffce1 100644 (file)
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -120,19 +120,19 @@ struct OzoneThreadState : public ThreadState {
         return miscRegFile.readReg(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+    MiscReg readMiscRegWithEffect(int misc_reg)
     {
         return miscRegFile.readRegWithEffect(misc_reg, fault, tc);
     }
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
-        return miscRegFile.setReg(misc_reg, val);
+        miscRegFile.setReg(misc_reg, val);
     }
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
-        return miscRegFile.setRegWithEffect(misc_reg, val, tc);
+        miscRegFile.setRegWithEffect(misc_reg, val, tc);
     }
 
     uint64_t readPC()

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 1d208b8df555f4933689c7979b591f225baed328..5c8d569bbf9e6bb49dff7fd23f052100e557c2fe 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -288,17 +288,17 @@ class BaseSimpleCPU : public BaseCPU
         return thread->readMiscReg(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+    MiscReg readMiscRegWithEffect(int misc_reg)
     {
-        return thread->readMiscRegWithEffect(misc_reg, fault);
+        return thread->readMiscRegWithEffect(misc_reg);
     }
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
         return thread->setMiscReg(misc_reg, val);
     }
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
         return thread->setMiscRegWithEffect(misc_reg, val);
     }

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index d005b2914f2fe14a81b1982741486cbe0e1c3b98..20f7f0d1c189d53a51342b663eed4e10ecda2c7c 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -420,17 +420,17 @@ class SimpleThread : public ThreadState
         return regs.readMiscReg(misc_reg);
     }
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+    MiscReg readMiscRegWithEffect(int misc_reg)
     {
-        return regs.readMiscRegWithEffect(misc_reg, fault, tc);
+        return regs.readMiscRegWithEffect(misc_reg, tc);
     }
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     {
         return regs.setMiscReg(misc_reg, val);
     }
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
         return regs.setMiscRegWithEffect(misc_reg, val, tc);
     }

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 448d67d024d82e60350bed56d758b4f313ecc52d..dfc6fbc2abdacd715cb88835348ce25302d407ef 100644 (file)
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -224,11 +224,11 @@ class ThreadContext
 
     virtual MiscReg readMiscReg(int misc_reg) = 0;
 
-    virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
+    virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0;
 
-    virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
+    virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
 
-    virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
+    virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
 
     // Also not necessarily the best location for these two.  Hopefully will go
     // away once we decide upon where st cond failures goes.
@@ -410,13 +410,13 @@ class ProxyThreadContext : public ThreadContext
     MiscReg readMiscReg(int misc_reg)
     { return actualTC->readMiscReg(misc_reg); }
 
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
-    { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
+    MiscReg readMiscRegWithEffect(int misc_reg)
+    { return actualTC->readMiscRegWithEffect(misc_reg); }
 
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val)
     { return actualTC->setMiscReg(misc_reg, val); }
 
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     { return actualTC->setMiscRegWithEffect(misc_reg, val); }
 
     unsigned readStCondFailures()