radeonsi/gfx10: enable primitive binning by default

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 1f924eaefb4b341db9e093afaa69b2b5037d2b8f..1070903fa32455b68feeb8846921570484694f57 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1127,11 +1127,13 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
                                           sscreen->info.chip_class >= GFX10;
 
        /* Only enable primitive binning on APUs by default. */
-       sscreen->dpbb_allowed = sscreen->info.chip_class >= GFX9 &&
-                               !sscreen->info.has_dedicated_vram;
-
-       sscreen->dfsm_allowed = sscreen->info.chip_class >= GFX9 &&
-                               !sscreen->info.has_dedicated_vram;
+       if (sscreen->info.chip_class >= GFX10) {
+               sscreen->dpbb_allowed = true;
+               sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
+       } else if (sscreen->info.chip_class == GFX9) {
+               sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
+               sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
+       }
 
        /* Process DPBB enable flags. */
        if (sscreen->debug_flags & DBG(DPBB)) {