Minor fixups to the sparc bmask/bshuffle patterns.

	* config/sparc/sparc.md (bmask<P:mode>_vis): Split into explicit 'di'
	and 'si' patterns which describe the GSR changes explicitly in the
	RTL using zero_extract.
	(bshuffle<V64I:mode>_vis): Put the GSR use inside of the unspec.

From-SVN: r179465

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 028ce8e12b77a2b45743275bcfe210f63f2b5c55..9fcee40ec132a11e836911333733ce855e45dc0d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2011-10-03  David S. Miller  <davem@davemloft.net>
+
+       * config/sparc/sparc.md (bmask<P:mode>_vis): Split into explicit 'di'
+       and 'si' patterns which describe the GSR changes explicitly in the
+       RTL using zero_extract.
+       (bshuffle<V64I:mode>_vis): Put the GSR use inside of the unspec.
+
 2011-10-03  Artem Shinkarov  <artyom.shinkaroff@gmail.com>
 
        * optabs.c (expand_vec_shuffle_expr_p): New function. Checks

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 699074682f660bef06de944f1ac8f6e833acf980..c48c979dba8fdd0a3ab107c38d74ce7810195092 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -8228,11 +8228,22 @@
   "array32\t%r1, %r2, %0"
   [(set_attr "type" "array")])
 
-(define_insn "bmask<P:mode>_vis"
-  [(set (match_operand:P 0 "register_operand" "=r")
-        (plus:P (match_operand:P 1 "register_operand" "rJ")
-                (match_operand:P 2 "register_operand" "rJ")))
-   (clobber (reg:SI GSR_REG))]
+(define_insn "bmaskdi_vis"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (plus:DI (match_operand:DI 1 "register_operand" "rJ")
+                 (match_operand:DI 2 "register_operand" "rJ")))
+   (set (zero_extract:DI (reg:DI GSR_REG) (const_int 32) (const_int 32))
+        (plus:DI (match_dup 1) (match_dup 2)))]
+  "TARGET_VIS2"
+  "bmask\t%r1, %r2, %0"
+  [(set_attr "type" "array")])
+
+(define_insn "bmasksi_vis"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (plus:SI (match_operand:SI 1 "register_operand" "rJ")
+                 (match_operand:SI 2 "register_operand" "rJ")))
+   (set (zero_extract:DI (reg:DI GSR_REG) (const_int 32) (const_int 32))
+        (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
   "TARGET_VIS2"
   "bmask\t%r1, %r2, %0"
   [(set_attr "type" "array")])
@@ -8240,9 +8251,9 @@
 (define_insn "bshuffle<V64I:mode>_vis"
   [(set (match_operand:V64I 0 "register_operand" "=e")
         (unspec:V64I [(match_operand:V64I 1 "register_operand" "e")
-                     (match_operand:V64I 2 "register_operand" "e")]
-                     UNSPEC_BSHUFFLE))
-   (use (reg:SI GSR_REG))]
+                     (match_operand:V64I 2 "register_operand" "e")
+                     (use (reg:SI GSR_REG))]
+                     UNSPEC_BSHUFFLE))]
   "TARGET_VIS2"
   "bshuffle\t%1, %2, %0"
   [(set_attr "type" "fga")