-fmove-all-movables -fno-default-inline -fno-defer-pop
-fno-function-cse -fno-inline -fno-peephole -ftrapv
-fomit-frame-pointer -foptimize-register-moves -foptimize-sibling-calls
--fregmove -frerun-cse-after-loop -frerun-loop-opt -freduce-all-givs
--fschedule-insns -fschedule-insns2 -fssa -fstrength-reduce
--fstrict-aliasing -fthread-jumps -funroll-all-loops
+-fregmove -frename-registers -frerun-cse-after-loop -frerun-loop-opt
+-freduce-all-givs -fschedule-insns -fschedule-insns2 -fssa
+-fstrength-reduce -fstrict-aliasing -fthread-jumps -funroll-all-loops
-funroll-loops
-O -O0 -O1 -O2 -O3 -Os
@end smallexample
As compared to @samp{-O}, this option increases both compilation time
and the performance of the generated code.
-@samp{-O2} turns on all optional optimizations except for loop unrolling
-and function inlining. It also turns on the @samp{-fforce-mem} option
-on all machines and frame pointer elimination on machines where doing so
-does not interfere with debugging.
+@samp{-O2} turns on all optional optimizations except for loop unrolling,
+function inlining, and register renaming. It also turns on the
+@samp{-fforce-mem} option on all machines and frame pointer elimination
+on machines where doing so does not interfere with debugging.
@item -O3
Optimize yet more. @samp{-O3} turns on all optimizations specified by
-@samp{-O2} and also turns on the @samp{inline-functions} option.
+@samp{-O2} and also turns on the @samp{-finline-functions} and
+@samp{-frename-registers} options.
@item -O0
Do not optimize.
-fno-delete-null-pointer-checks to disable this optimizing for programs
which depend on that behavior.
-
@item -fexpensive-optimizations
Perform a number of minor optimizations that are relatively expensive.
Treat floating point constant as single precision constant instead of
implicitly converting it to double precision constant.
+@item -frename-registers
+Attempt to avoid false dependancies in scheduled code by making use
+of registers left over after register allocation. This optimization
+will most benefit processors with lots of registers. It can, however,
+make debugging impossible, since variables will no longer stay in
+a ``home register''.
@end table
@node Preprocessor Options
DFI_lreg,
DFI_greg,
DFI_flow2,
- DFI_ce2,
DFI_peephole2,
DFI_rnreg,
+ DFI_ce2,
DFI_sched2,
DFI_bbro,
DFI_jump2,
{ "lreg", 'l', 1, 0, 0 },
{ "greg", 'g', 1, 0, 0 },
{ "flow2", 'w', 1, 0, 0 },
- { "ce2", 'E', 1, 0, 0 },
{ "peephole2", 'z', 1, 0, 0 },
{ "rnreg", 'n', 1, 0, 0 },
+ { "ce2", 'E', 1, 0, 0 },
{ "sched2", 'R', 1, 0, 0 },
{ "bbro", 'B', 1, 0, 0 },
{ "jump2", 'J', 1, 0, 0 },
close_dump_file (DFI_flow2, print_rtl_with_bb, insns);
timevar_pop (TV_FLOW2);
- if (optimize > 0)
- {
- timevar_push (TV_IFCVT2);
- open_dump_file (DFI_ce2, decl);
-
- if_convert (1);
-
- close_dump_file (DFI_ce2, print_rtl_with_bb, insns);
- timevar_pop (TV_IFCVT2);
- }
-
#ifdef HAVE_peephole2
if (optimize > 0 && flag_peephole2)
{
timevar_pop (TV_RENAME_REGISTERS);
}
+ if (optimize > 0)
+ {
+ timevar_push (TV_IFCVT2);
+ open_dump_file (DFI_ce2, decl);
+
+ if_convert (1);
+
+ close_dump_file (DFI_ce2, print_rtl_with_bb, insns);
+ timevar_pop (TV_IFCVT2);
+ }
+
#ifdef INSN_SCHEDULING
if (optimize > 0 && flag_schedule_insns_after_reload)
{
if (optimize >= 3)
{
flag_inline_functions = 1;
+ flag_rename_registers = 1;
}
if (optimize < 2 || optimize_size)