+2006-07-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/opcode.s: Add sldt, smsw and str.
+ * gas/i386/x86-64-opcode.s: Likewise.
+
+ * gas/i386/opcode.d: Updated.
+ * gas/i386/x86-64-opcode.d: Likewise.
+
2006-07-18 Paul Brook <paul@codesourcery.com>
* gas/arm/thumb2_add.d: New test.
9bf: 66 0f be 90 90 90 90 90 [ ]*movsbw 0x90909090\(%eax\),%dx
9c7: 66 0f c1 90 90 90 90 90 [ ]*xadd %dx,0x90909090\(%eax\)
9cf: 66 90 [ ]*xchg %ax,%ax
+ 9d1: 0f 00 c0 [ ]*sldt %eax
+ 9d4: 66 0f 00 c0 [ ]*sldt %ax
+ 9d8: 0f 00 00 [ ]*sldt \(%eax\)
+ 9db: 0f 01 e0 [ ]*smsw %eax
+ 9de: 66 0f 01 e0 [ ]*smsw %ax
+ 9e2: 0f 01 20 [ ]*smsw \(%eax\)
+ 9e5: 0f 00 c8 [ ]*str %eax
+ 9e8: 66 0f 00 c8 [ ]*str %ax
+ 9ec: 0f 00 08 [ ]*str \(%eax\)
\.\.\.
xchg %ax,%ax
+ sldt %eax
+ sldt %ax
+ sldt (%eax)
+ smsw %eax
+ smsw %ax
+ smsw (%eax)
+ str %eax
+ str %ax
+ str (%eax)
+
# Force a good alignment.
.p2align 4,0
[ ]*[0-9a-f]+:[ ]+41 0f 01 38[ ]+invlpg[ ]+\(%r8\)[ ]*(#.*)*
[ ]*[0-9a-f]+:[ ]+0f 01 38[ ]+invlpg[ ]+\(%rax\)[ ]*(#.*)*
[ ]*[0-9a-f]+:[ ]+0f 00 c0[ ]+sldt[ ]+%eax[ ]*(#.*)*
+[ ]*[0-9a-f]+:[ ]+48 0f 00 c0[ ]+sldt[ ]+%rax[ ]*(#.*)*
+[ ]*[0-9a-f]+:[ ]+66 0f 00 c0[ ]+sldt[ ]+%ax[ ]*(#.*)*
+[ ]*[0-9a-f]+:[ ]+0f 00 00[ ]+sldt[ ]+\(%rax\)[ ]*(#.*)*
[ ]*[0-9a-f]+:[ ]+e6 00[ ]+out[ ]+%al,\$0[x0]*[ ]*(#.*)*
[ ]*[0-9a-f]+:[ ]+66 e7 00[ ]+out[ ]+%ax,\$0[x0]*[ ]*(#.*)*
[ ]*[0-9a-f]+:[ ]+e7 00[ ]+out[ ]+%eax,\$0[x0]*[ ]*(#.*)*
[ ]*[0-9a-f]+:[ ]+90[ ]+nop[ ]*(#.*)*
[ ]*[0-9a-f]+:[ ]+48 90[ ]+rex64 nop[ ]*(#.*)*
[ ]*[0-9a-f]+:[ ]+49 90[ ]+xchg[ ]+%rax,%r8[ ]*(#.*)*
+[ ]*[0-9a-f]+:[ ]+48 0f 01 e0[ ]+smsw[ ]+%rax[ ]*(#.*)*
+[ ]*[0-9a-f]+:[ ]+0f 01 e0[ ]+smsw[ ]+%eax[ ]*(#.*)*
+[ ]*[0-9a-f]+:[ ]+66 0f 01 e0[ ]+smsw[ ]+%ax[ ]*(#.*)*
+[ ]*[0-9a-f]+:[ ]+0f 01 20[ ]+smsw[ ]+\(%rax\)[ ]*(#.*)*
+[ ]*[0-9a-f]+:[ ]+48 0f 00 c8[ ]+str[ ]+%rax[ ]*(#.*)*
+[ ]*[0-9a-f]+:[ ]+0f 00 c8[ ]+str[ ]+%eax[ ]*(#.*)*
+[ ]*[0-9a-f]+:[ ]+66 0f 00 c8[ ]+str[ ]+%ax[ ]*(#.*)*
+[ ]*[0-9a-f]+:[ ]+0f 00 08[ ]+str[ ]+\(%rax\)[ ]*(#.*)*
#pass
# SLDT
# SLDT (%eax) # -- 67 -- -- 0F 00 00 ; A32 override: (Addr64) = ZEXT(Addr32 )
SLDT %eax # -- -- -- -- 0F 00 C0
+ SLDT %rax # -- -- -- 48 0F 00 C0
+ SLDT %ax # 66 -- -- -- 0F 00 C0
+ SLDT (%rax) # -- -- -- -- 0F 00 00
# SWAPGS
xchg %ax,%ax # 66 -- -- -- 90
xchg %eax,%eax # -- -- -- -- 87 C0
xchg %rax,%rax # -- -- -- -- 90
- rex64 xchg %rax,%rax # 48 -- -- -- 90
+ rex64 xchg %rax,%rax # -- -- -- 48 90
xchg %rax,%r8 # -- -- -- 49 90
+ smsw %rax # -- -- -- 48 0F 01 e0
+ smsw %eax # -- -- -- -- 0F 01 e0
+ smsw %ax # 66 -- -- -- 0F 01 e0
+ smsw (%rax) # -- -- -- -- 0F 01 20
+
+ str %rax # -- -- -- 48 0F 00 c8
+ str %eax # -- -- -- -- 0F 00 c8
+ str %ax # 66 -- -- -- 0F 00 c8
+ str (%rax) # -- -- -- -- 0F 00 08
+
.p2align 4,0
+2006-07-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
+ "sldt", "str" and "smsw".
+
2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/2829
},
/* GRP6 */
{
- { "sldtQ", Ev, XX, XX, XX },
- { "strQ", Ev, XX, XX, XX },
+ { "sldt", Ev, XX, XX, XX },
+ { "str", Ev, XX, XX, XX },
{ "lldt", Ew, XX, XX, XX },
{ "ltr", Ew, XX, XX, XX },
{ "verr", Ew, XX, XX, XX },
{ "sidt{Q|IQ||}", PNI_Fixup, 0, XX, XX, XX },
{ "lgdt{Q|Q||}", M, XX, XX, XX },
{ "lidt{Q|Q||}", SVME_Fixup, 0, XX, XX, XX },
- { "smswQ", Ev, XX, XX, XX },
+ { "smsw", Ev, XX, XX, XX },
{ "(bad)", XX, XX, XX, XX },
{ "lmsw", Ew, XX, XX, XX },
{ "invlpg", INVLPG_Fixup, w_mode, XX, XX, XX },