unsigned use_blt : 1;
/* can use any kind of wrapping mode on npot textures */
unsigned npot_tex_any_wrap : 1;
+ /* supports seamless cube map */
+ unsigned seamless_cube_map : 1;
/* number of bits per TS tile */
unsigned bits_per_tile;
/* clear value for TS (dependent on bits_per_tile) */
case PIPE_CAP_MAX_TEXEL_OFFSET:
return 7;
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
- return VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP);
+ return screen->specs.seamless_cube_map;
/* Timer queries. */
case PIPE_CAP_OCCLUSION_QUERY:
VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
screen->specs.v4_compression =
VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION);
+ screen->specs.seamless_cube_map =
+ (screen->model != 0x880) && /* Seamless cubemap is broken on GC880? */
+ VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP);
if (screen->specs.halti >= 5) {
/* GC7000 - this core must load shaders from memory. */
const struct pipe_sampler_state *ss)
{
struct etna_sampler_state *cs = CALLOC_STRUCT(etna_sampler_state);
+ struct etna_context *ctx = etna_context(pipe);
+ struct etna_screen *screen = ctx->screen;
const bool ansio = ss->max_anisotropy > 1;
if (!cs)
cs->TE_SAMPLER_CONFIG0 |= VIVS_TE_SAMPLER_CONFIG0_ROUND_UV;
}
- cs->TE_SAMPLER_CONFIG1 =
- COND(ss->seamless_cube_map, VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP);
+ cs->TE_SAMPLER_CONFIG1 = screen->specs.seamless_cube_map ?
+ COND(ss->seamless_cube_map, VIVS_TE_SAMPLER_CONFIG1_SEAMLESS_CUBE_MAP) : 0;
cs->TE_SAMPLER_LOD_CONFIG =
COND(ss->lod_bias != 0.0, VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE) |