cpu-minor: fix store-release issuing

Store with release flag are treated like store conditionals and are not
bufferable. Also they are only sent when the store buffer is empty to
satisfy the release semantics.

Change-Id: I253ec5ecd39901b14d0dc8efbc82cf7e4b07f08f
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27135
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>

diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index e50d49832d7e9382bab5066d4d6eeecdfdaa4af4..e4a9dc024e012415e6da24afe30a3d185998ed0d 100644 (file)
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014,2017-2018 ARM Limited
+ * Copyright (c) 2013-2014,2017-2018,2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -1029,10 +1029,11 @@ LSQ::tryToSendToTransfers(LSQRequestPtr request)
 
     bool is_load = request->isLoad;
     bool is_llsc = request->request->isLLSC();
+    bool is_release = request->request->isRelease();
     bool is_swap = request->request->isSwap();
     bool is_atomic = request->request->isAtomic();
     bool bufferable = !(request->request->isStrictlyOrdered() ||
-                        is_llsc || is_swap || is_atomic);
+                        is_llsc || is_swap || is_atomic || is_release);
 
     if (is_load) {
         if (numStoresInTransfers != 0) {
@@ -1050,6 +1051,15 @@ LSQ::tryToSendToTransfers(LSQRequestPtr request)
         }
     }
 
+    // Process store conditionals or store release after all previous
+    // stores are completed
+    if (((!is_load && is_llsc) || is_release) &&
+        !storeBuffer.isDrained()) {
+        DPRINTF(MinorMem, "Memory access needs to wait for store buffer"
+                          " to drain\n");
+        return;
+    }
+
     /* Check if this is the head instruction (and so must be executable as
      *  its stream sequence number was checked above) for loads which must
      *  not be speculatively issued and stores which must be issued here */