targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix...

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 501a8d7ec91b58c14f4672f43d196f70620e0ae4..fcb2a4f6e17e4cf7d40493ddf227a38132b36948 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -136,7 +136,8 @@ class MiniSoC(BaseSoC):
 
         self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"),
                                                self.platform.request("eth"))
-        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness="little")
+        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
+            interface="wishbone", endianness=self.cpu_endianness)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index b42743e503e2e33bd0859d9bdf7ed1e0abccef85..460f0e47f570759b0eccdeb9450c0436f8188764 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -118,7 +118,8 @@ class MiniSoC(BaseSoC):
 
         self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
                                                  self.platform.request("eth"))
-        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
+        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
+            interface="wishbone", endianness=self.cpu_endianness)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 89498d67517a0655a8f8106c4ca27c708cab3e6d..514c33e84d9991c011a9ec645bde048fe9da46fa 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -118,7 +118,8 @@ class MiniSoC(BaseSoC):
 
         self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"),
                                             self.platform.request("eth"), clk_freq=self.clk_freq)
-        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
+        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
+            interface="wishbone", endianness=self.cpu_endianness)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index e0146fbb43dc018a2662bff438191181c79347fa..3a97e2aac5c6be92b83906ec914fd7cca18ff26c 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -125,7 +125,8 @@ class MiniSoC(BaseSoC):
 
         self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
                                                  self.platform.request("eth"))
-        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
+        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
+            interface="wishbone", endianness=self.cpu_endianness)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index 1cd08bd67bfaf04d7f2bd162033dbbac766c49fc..d62ecdf956169de743596e1a5a3ec454f35fb7cb 100755 (executable)
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -87,7 +87,8 @@ class MiniSoC(BaseSoC):
         BaseSoC.__init__(self, *args, **kwargs)
 
         self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
-        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
+        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
+            interface="wishbone", endianness=self.cpu_endianness)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 

diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index ccc8cbc3cd3fb287cb39efd840223a94593d3576..8577a04a1c4a1b645f524b5b91c9b3fe7a837123 100755 (executable)
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -45,8 +45,7 @@ class MiniSoC(BaseSoC):
         self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
                                             platform.request("eth"))
         self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
-                                            interface="wishbone",
-                                            with_preamble_crc=False)
+            interface="wishbone", endianness=self.cpu_endianness, with_preamble_crc=False)
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 

diff --git a/litex/soc/software/libnet/microudp.c b/litex/soc/software/libnet/microudp.c
index b54107101bf950eb9b723053318935fee3697549..38e16588bd0d4ede15cc172e1c466c63db0c9e78 100644 (file)
--- a/litex/soc/software/libnet/microudp.c
+++ b/litex/soc/software/libnet/microudp.c
@@ -127,6 +127,7 @@ static ethernet_buffer *txbuffer1;
 
 static void send_packet(void)
 {
+
 #ifndef HW_PREAMBLE_CRC
        unsigned int crc;
        crc = crc32(&txbuffer->raw[8], txlen-8);
@@ -134,9 +135,9 @@ static void send_packet(void)
        txbuffer->raw[txlen+1] = (crc & 0xff00) >> 8;
        txbuffer->raw[txlen+2] = (crc & 0xff0000) >> 16;
        txbuffer->raw[txlen+3] = (crc & 0xff000000) >> 24;
-       //txlen += 4;
+       txlen += 4;
 #endif
-       txlen += 4; // FIXME
+       txlen += 4; //FIXME: padding?
 
 #ifdef DEBUG_MICROUDP_TX
        int j;
@@ -169,7 +170,7 @@ static void process_arp(void)
        const struct arp_frame *rx_arp = &rxbuffer->frame.contents.arp;
        struct arp_frame *tx_arp = &txbuffer->frame.contents.arp;
 
-       //if(rxlen < ARP_PACKET_LENGTH) return; // FIXME
+       if(rxlen < ARP_PACKET_LENGTH) return;
        if(ntohs(rx_arp->hwtype) != ARP_HWTYPE_ETHERNET) return;
        if(ntohs(rx_arp->proto) != ARP_PROTO_IP) return;
        if(rx_arp->hwsize != 6) return;