[ARC] ISA alignment.

include/
2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (insn_class_t): Add two new classes.

opcodes/
2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-ext-tbl.h (EXTINSN2OPF): Define.
	(EXTINSN2OP): Use EXTINSN2OPF.
	(bspeekm, bspop, modapp): New extension instructions.
	* arc-opc.c (F_DNZ_ND): Define.
	(F_DNZ_D): Likewise.
	(F_SIZEB1): Changed.
	(C_DNZ_D): Define.
	(C_HARD): Changed.
	* arc-tbl.h (dbnz): New instruction.
	(prealloc): Allow it for ARC EM.
	(xbfu): Likewise.

diff --git a/include/ChangeLog b/include/ChangeLog
index 28ab8919eece3ab8ff2f6bb8ebd679d6a76a6299..01d1c1416c24afb4d231d70e41c6fdfd6fe8f00c 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * opcode/arc.h (insn_class_t): Add two new classes.
+
 2016-09-26  Alan Modra  <amodra@gmail.com>
 
        * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment on new values.

diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index faa63dcdcbec60fca15642f4bf65c7c60bd1c8bb..09e973bdf5f29ea1d6e570cbb3f8f6802e371adb 100644 (file)
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -43,6 +43,7 @@ typedef enum
   ARITH,
   AUXREG,
   BITOP,
+  BITSTREAM,
   BMU,
   BRANCH,
   CONTROL,
@@ -55,7 +56,8 @@ typedef enum
   LOGICAL,
   MEMORY,
   NET,
-  PMU
+  PMU,
+  XY
 } insn_class_t;
 
 /* Instruction Subclass.  */

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c712058bb4dcf3acd050d632577105355dab9c10..282b4768dfd35b2dd6d298bf98d7e4e140b2437a 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,17 @@
+2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * arc-ext-tbl.h (EXTINSN2OPF): Define.
+       (EXTINSN2OP): Use EXTINSN2OPF.
+       (bspeekm, bspop, modapp): New extension instructions.
+       * arc-opc.c (F_DNZ_ND): Define.
+       (F_DNZ_D): Likewise.
+       (F_SIZEB1): Changed.
+       (C_DNZ_D): Define.
+       (C_HARD): Changed.
+       * arc-tbl.h (dbnz): New instruction.
+       (prealloc): Allow it for ARC EM.
+       (xbfu): Likewise.
+
 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 
        * aarch64-opc.c (print_immediate_offset_address): Print spaces

diff --git a/opcodes/arc-ext-tbl.h b/opcodes/arc-ext-tbl.h
index 3fb1c11856679cb566e6a2ff0026d70676ad00b8..e77e9687771aa5689379ba4780177ac07ffe67e2 100644 (file)
--- a/opcodes/arc-ext-tbl.h
+++ b/opcodes/arc-ext-tbl.h
@@ -55,19 +55,22 @@
 #define ARG_32BIT_ZALIMM { ZA, LIMM }
 
 /* Macro to generate 2 operand extension instruction.  */
-#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP)          \
+#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL)     \
   { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \
-      ARG_32BIT_RBRC,   FLAGS_F },                              \
+      ARG_32BIT_RBRC,   FL },                                   \
   { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \
-      ARG_32BIT_ZARC,   FLAGS_F },                              \
+      ARG_32BIT_ZARC,   FL },                                   \
   { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \
-      ARG_32BIT_RBU6,   FLAGS_F },                              \
+      ARG_32BIT_RBU6,   FL },                                   \
   { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \
-      ARG_32BIT_ZAU6,   FLAGS_F },                              \
+      ARG_32BIT_ZAU6,   FL },                                   \
   { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \
-      ARG_32BIT_RBLIMM, FLAGS_F },                              \
+      ARG_32BIT_RBLIMM, FL },                                   \
   { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \
-      ARG_32BIT_ZALIMM, FLAGS_F },
+      ARG_32BIT_ZALIMM, FL },
+
+#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP)          \
+  EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F)
 
 /* Macro to generate 3 operand extesion instruction.  */
 #define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP)                 \
@@ -120,3 +123,9 @@ EXTINSN2OP ("dsp_fp_sqrt",   ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 45)
 EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 42)
 EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE, 7, 43)
 
+/* Bitstream extensions.  */
+EXTINSN2OP ("bspeek", ARC_OPCODE_ARCv2EM, BITSTREAM, NONE, 0x05, 0x2E)
+EXTINSN2OP ("bspop", ARC_OPCODE_ARCv2EM, BITSTREAM, NONE, 0x05, 0x2F)
+
+/* Special XY.  */
+EXTINSN2OPF ("modapp", ARC_OPCODE_ARCv2EM, XY, NONE, 0x05, 0x3E, FLAGS_NONE)

diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 44dd7b2d32a0f3763e4a8449ac9923502497c2aa..65373104687ae37ff3fad44374c085270e6e5e52 100644 (file)
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1279,9 +1279,13 @@ const struct arc_flag_operand arc_flag_operands[] =
   { "d",  1, 1, 5, 1 },
 #define F_DFAKE           (F_D + 1)
   { "d",  0, 0, 0, 1 },
+#define F_DNZ_ND   (F_DFAKE + 1)
+  { "nd", 0, 1, 16, 0 },
+#define F_DNZ_D           (F_DNZ_ND + 1)
+  { "d",  1, 1, 16, 1 },
 
   /* Data size.  */
-#define F_SIZEB1   (F_DFAKE + 1)
+#define F_SIZEB1   (F_DNZ_D + 1)
   { "b", 1, 2, 1, 1 },
 #define F_SIZEB7   (F_SIZEB1 + 1)
   { "b", 1, 2, 7, 1 },
@@ -1485,8 +1489,10 @@ const struct arc_flag_class arc_flag_classes[] =
   { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
 #define C_D        (C_T + 1)
   { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
+#define C_DNZ_D     (C_D + 1)
+  { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
 
-#define C_DHARD            (C_D + 1)
+#define C_DHARD            (C_DNZ_D + 1)
   { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
 
 #define C_DI20     (C_DHARD + 1)

diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index 7bda40a9c4e5f2edce2ea1c76f6e95cfd6e78187..682b808a5be6ad27ba732190b9ba53649f5779ca 100644 (file)
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -3499,6 +3499,9 @@
 /* daddh22<.f><.cc> 0,limm,limm 0011011011110111F1111111100QQQQQ.  */
 { "daddh22", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DPA, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
 
+/* dbnz<.d> b,s13 00100bbb1000110N0BBBssssssSSSSSS.  */
+{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, SIMM13_A16_20}, { C_DNZ_D }},
+
 /* dexcl1<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA.  */
 { "dexcl1", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DPX, { RA, RB, RC }, { C_F }},
 
@@ -12985,22 +12988,22 @@
 { "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BLINK_S }, { 0 }},
 
 /* prealloc<.aa> b,c 00100bbbaa1100010BBBCCCCCC111110.  */
-{ "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
+{ "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
 
 /* prealloc<.aa> b,s9 00010bbbssssssssSBBB0aa001111110.  */
-{ "prealloc", 0x1000007E, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }},
+{ "prealloc", 0x1000007E, 0xF80009FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }},
 
 /* prealloc<.aa> b,limm 00100bbbaa1100010BBB111110111110.  */
-{ "prealloc", 0x20310FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }},
+{ "prealloc", 0x20310FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }},
 
 /* prealloc limm,c 00100110RR1100010111CCCCCC111110.  */
-{ "prealloc", 0x2631703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }},
+{ "prealloc", 0x2631703E, 0xFF3FF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }},
 
 /* prealloc limm 000101100000000001110RR001111110.  */
-{ "prealloc", 0x1600707E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+{ "prealloc", 0x1600707E, 0xFFFFF9FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
 
 /* prealloc limm,s9 00010110ssssssssS1110RR001111110.  */
-{ "prealloc", 0x1600707E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
+{ "prealloc", 0x1600707E, 0xFF0079FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
 
 /* prefetch<.aa> b,c 00100bbbaa1100000BBBCCCCCC111110.  */
 { "prefetch", 0x2030003E, 0xF83F803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
@@ -18061,64 +18064,64 @@
 { "wlfc", 0x216F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_20 }, { 0 }},
 
 /* xbfu<.f> a,b,c 00100bbb00101101FBBBCCCCCCAAAAAA.  */
-{ "xbfu", 0x202D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, RC }, { C_F }},
+{ "xbfu", 0x202D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, RC }, { C_F }},
 
 /* xbfu<.f> 0,b,c 00100bbb00101101FBBBCCCCCC111110.  */
-{ "xbfu", 0x202D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, RC }, { C_F }},
+{ "xbfu", 0x202D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, RC }, { C_F }},
 
 /* xbfu<.f><.cc> b,b,c 00100bbb11101101FBBBCCCCCC0QQQQQ.  */
-{ "xbfu", 0x20ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+{ "xbfu", 0x20ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
 
 /* xbfu<.f> a,b,u6 00100bbb01101101FBBBuuuuuuAAAAAA.  */
-{ "xbfu", 0x206D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+{ "xbfu", 0x206D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
 
 /* xbfu<.f> 0,b,u6 00100bbb01101101FBBBuuuuuu111110.  */
-{ "xbfu", 0x206D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+{ "xbfu", 0x206D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
 
 /* xbfu<.f><.cc> b,b,u6 00100bbb11101101FBBBuuuuuu1QQQQQ.  */
-{ "xbfu", 0x20ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+{ "xbfu", 0x20ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
 
 /* xbfu<.f> b,b,s12 00100bbb10101101FBBBssssssSSSSSS.  */
-{ "xbfu", 0x20AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+{ "xbfu", 0x20AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
 
 /* xbfu<.f> a,limm,c 0010011000101101F111CCCCCCAAAAAA.  */
-{ "xbfu", 0x262D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, RC }, { C_F }},
+{ "xbfu", 0x262D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, RC }, { C_F }},
 
 /* xbfu<.f> a,b,limm 00100bbb00101101FBBB111110AAAAAA.  */
-{ "xbfu", 0x202D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, LIMM }, { C_F }},
+{ "xbfu", 0x202D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, LIMM }, { C_F }},
 
 /* xbfu<.f> 0,limm,c 0010011000101101F111CCCCCC111110.  */
-{ "xbfu", 0x262D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F }},
+{ "xbfu", 0x262D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F }},
 
 /* xbfu<.f> 0,b,limm 00100bbb00101101FBBB111110111110.  */
-{ "xbfu", 0x202D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, LIMM }, { C_F }},
+{ "xbfu", 0x202D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, LIMM }, { C_F }},
 
 /* xbfu<.f><.cc> b,b,limm 00100bbb11101101FBBB1111100QQQQQ.  */
-{ "xbfu", 0x20ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+{ "xbfu", 0x20ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
 
 /* xbfu<.f><.cc> 0,limm,c 0010011011101101F111CCCCCC0QQQQQ.  */
-{ "xbfu", 0x26ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+{ "xbfu", 0x26ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
 
 /* xbfu<.f> a,limm,u6 0010011001101101F111uuuuuuAAAAAA.  */
-{ "xbfu", 0x266D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "xbfu", 0x266D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
 
 /* xbfu<.f> 0,limm,u6 0010011001101101F111uuuuuu111110.  */
-{ "xbfu", 0x266D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+{ "xbfu", 0x266D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
 
 /* xbfu<.f><.cc> 0,limm,u6 0010011011101101F111uuuuuu1QQQQQ.  */
-{ "xbfu", 0x26ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+{ "xbfu", 0x26ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
 
 /* xbfu<.f> 0,limm,s12 0010011010101101F111ssssssSSSSSS.  */
-{ "xbfu", 0x26AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+{ "xbfu", 0x26AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
 
 /* xbfu<.f> a,limm,limm 0010011000101101F111111110AAAAAA.  */
-{ "xbfu", 0x262D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+{ "xbfu", 0x262D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
 
 /* xbfu<.f> 0,limm,limm 0010011000101101F111111110111110.  */
-{ "xbfu", 0x262D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+{ "xbfu", 0x262D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
 
 /* xbfu<.f><.cc> 0,limm,limm 0010011011101101F1111111100QQQQQ.  */
-{ "xbfu", 0x26ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+{ "xbfu", 0x26ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
 
 /* xor<.f> a,b,c 00100bbb00000111FBBBCCCCCCAAAAAA.  */
 { "xor", 0x20070000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},