Use common definition for FinalizeError

diff --git a/migen/bus/asmibus.py b/migen/bus/asmibus.py
index cab327a7d5239d7724706984d4f5d08a0a8fb470..6f639e9575524f6f239d859bf2913af5326b3d42 100644 (file)
--- a/migen/bus/asmibus.py
+++ b/migen/bus/asmibus.py
@@ -3,9 +3,6 @@ from migen.genlib.misc import optree
 from migen.bus.transactions import *
 from migen.sim.generic import Proxy, PureSimulable
 
-class FinalizeError(Exception):
-       pass
-
 (SLOT_EMPTY, SLOT_PENDING, SLOT_PROCESSING) = range(3)
 
 class Slot:

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 8052fdffbbc700e473247c8dab0f8ecd2643ec15..3b5ca53e978b17f7f359580a83a32b5a886a5816 100644 (file)
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -276,3 +276,6 @@ class ClockDomain:
                        n_rst = n2
                self.clk = Signal(name_override=n_clk)
                self.rst = Signal(name_override=n_rst)
+
+class FinalizeError(Exception):
+       pass

diff --git a/migen/pytholite/reg.py b/migen/pytholite/reg.py
index 5ec49c4a9d5723fac6a53021d4cab38c26fea36f..6346753d0e0a40cd8bfc411a75d337741baf328b 100644 (file)
--- a/migen/pytholite/reg.py
+++ b/migen/pytholite/reg.py
@@ -3,9 +3,6 @@ from operator import itemgetter
 from migen.fhdl.structure import *
 from migen.fhdl import visit as fhdl
 
-class FinalizeError(Exception):
-       pass
-
 class AbstractLoad:
        def __init__(self, target, source):
                self.target = target