struct ShregmapWorker
{
- Module *module;
- SigMap sigmap;
+ Module *module;
+ SigMap sigmap;
- const ShregmapOptions &opts;
- int dff_count, shreg_count;
-
- pool<Cell*> remove_cells;
- pool<SigBit> remove_init;
+ const ShregmapOptions &opts;
+ int dff_count, shreg_count;
- dict<SigBit, bool> sigbit_init;
- dict<SigBit, Cell*> sigbit_chain_next;
- dict<SigBit, Cell*> sigbit_chain_prev;
- pool<SigBit> sigbit_with_non_chain_users;
- pool<Cell*> chain_start_cells;
+ pool<Cell*> remove_cells;
+ pool<SigBit> remove_init;
- void make_sigbit_chain_next_prev()
- {
- for (auto wire : module->wires())
- {
- if (wire->port_output || wire->get_bool_attribute("\\keep")) {
- for (auto bit : sigmap(wire)) {
- sigbit_with_non_chain_users.insert(bit);
- if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
- }
- }
-
- if (wire->attributes.count("\\init")) {
- SigSpec initsig = sigmap(wire);
- Const initval = wire->attributes.at("\\init");
- for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
- if (initval[i] == State::S0 && !opts.zinit)
- sigbit_init[initsig[i]] = false;
- else if (initval[i] == State::S1)
- sigbit_init[initsig[i]] = true;
- }
- }
+ dict<SigBit, bool> sigbit_init;
+ dict<SigBit, Cell*> sigbit_chain_next;
+ dict<SigBit, Cell*> sigbit_chain_prev;
+ pool<SigBit> sigbit_with_non_chain_users;
+ pool<Cell*> chain_start_cells;
- for (auto cell : module->cells())
+ void make_sigbit_chain_next_prev()
{
- if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep"))
- {
- IdString d_port = opts.ffcells.at(cell->type).first;
- IdString q_port = opts.ffcells.at(cell->type).second;
+ for (auto wire : module->wires())
+ {
+ if (wire->port_output || wire->get_bool_attribute("\\keep")) {
+ for (auto bit : sigmap(wire)) {
+ sigbit_with_non_chain_users.insert(bit);
+ if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
+ }
+ }
- SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
- SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
+ if (wire->attributes.count("\\init")) {
+ SigSpec initsig = sigmap(wire);
+ Const initval = wire->attributes.at("\\init");
+ for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
+ if (initval[i] == State::S0 && !opts.zinit)
+ sigbit_init[initsig[i]] = false;
+ else if (initval[i] == State::S1)
+ sigbit_init[initsig[i]] = true;
+ }
+ }
- if (opts.init || sigbit_init.count(q_bit) == 0)
+ for (auto cell : module->cells())
{
- if (sigbit_chain_next.count(d_bit)) {
- sigbit_with_non_chain_users.insert(d_bit);
- } else
- sigbit_chain_next[d_bit] = cell;
+ if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep"))
+ {
+ IdString d_port = opts.ffcells.at(cell->type).first;
+ IdString q_port = opts.ffcells.at(cell->type).second;
+
+ SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
+ SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
+
+ if (opts.init || sigbit_init.count(q_bit) == 0)
+ {
+ if (sigbit_chain_next.count(d_bit)) {
+ sigbit_with_non_chain_users.insert(d_bit);
+ } else
+ sigbit_chain_next[d_bit] = cell;
+
+ sigbit_chain_prev[q_bit] = cell;
+ continue;
+ }
+ }
- sigbit_chain_prev[q_bit] = cell;
- continue;
+ for (auto conn : cell->connections())
+ if (cell->input(conn.first))
+ for (auto bit : sigmap(conn.second)) {
+ sigbit_with_non_chain_users.insert(bit);
+ if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first);
+ }
}
- }
-
- for (auto conn : cell->connections())
- if (cell->input(conn.first))
- for (auto bit : sigmap(conn.second)) {
- sigbit_with_non_chain_users.insert(bit);
- if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first);
- }
}
- }
- void find_chain_start_cells()
- {
- for (auto it : sigbit_chain_next)
+ void find_chain_start_cells()
{
- if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
- goto start_cell;
+ for (auto it : sigbit_chain_next)
+ {
+ if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
+ goto start_cell;
- if (sigbit_chain_prev.count(it.first) != 0)
- {
- Cell *c1 = sigbit_chain_prev.at(it.first);
- Cell *c2 = it.second;
+ if (sigbit_chain_prev.count(it.first) != 0)
+ {
+ Cell *c1 = sigbit_chain_prev.at(it.first);
+ Cell *c2 = it.second;
- if (c1->type != c2->type)
- goto start_cell;
+ if (c1->type != c2->type)
+ goto start_cell;
- if (c1->parameters != c2->parameters)
- goto start_cell;
+ if (c1->parameters != c2->parameters)
+ goto start_cell;
- IdString d_port = opts.ffcells.at(c1->type).first;
- IdString q_port = opts.ffcells.at(c1->type).second;
+ IdString d_port = opts.ffcells.at(c1->type).first;
+ IdString q_port = opts.ffcells.at(c1->type).second;
- auto c1_conn = c1->connections();
- auto c2_conn = c1->connections();
+ auto c1_conn = c1->connections();
+ auto c2_conn = c1->connections();
- c1_conn.erase(d_port);
- c1_conn.erase(q_port);
+ c1_conn.erase(d_port);
+ c1_conn.erase(q_port);
- c2_conn.erase(d_port);
- c2_conn.erase(q_port);
+ c2_conn.erase(d_port);
+ c2_conn.erase(q_port);
- if (c1_conn != c2_conn)
- goto start_cell;
+ if (c1_conn != c2_conn)
+ goto start_cell;
- continue;
- }
+ continue;
+ }
-start_cell:
- chain_start_cells.insert(it.second);
+ start_cell:
+ chain_start_cells.insert(it.second);
+ }
}
- }
- vector<Cell*> create_chain(Cell *start_cell)
- {
- vector<Cell*> chain;
-
- Cell *c = start_cell;
- while (c != nullptr)
+ vector<Cell*> create_chain(Cell *start_cell)
{
- chain.push_back(c);
+ vector<Cell*> chain;
- IdString q_port = opts.ffcells.at(c->type).second;
- SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
+ Cell *c = start_cell;
+ while (c != nullptr)
+ {
+ chain.push_back(c);
- if (sigbit_chain_next.count(q_bit) == 0)
- break;
+ IdString q_port = opts.ffcells.at(c->type).second;
+ SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
- c = sigbit_chain_next.at(q_bit);
- if (chain_start_cells.count(c) != 0)
- break;
- }
+ if (sigbit_chain_next.count(q_bit) == 0)
+ break;
- return chain;
- }
+ c = sigbit_chain_next.at(q_bit);
+ if (chain_start_cells.count(c) != 0)
+ break;
+ }
- void process_chain(vector<Cell*> &chain)
- {
- if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
- return;
+ return chain;
+ }
- int cursor = opts.keep_before;
- while (cursor < GetSize(chain) - opts.keep_after)
+ void process_chain(vector<Cell*> &chain)
{
- int depth = GetSize(chain) - opts.keep_after - cursor;
+ if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
+ return;
- if (opts.maxlen > 0)
- depth = std::min(opts.maxlen, depth);
+ int cursor = opts.keep_before;
+ while (cursor < GetSize(chain) - opts.keep_after)
+ {
+ int depth = GetSize(chain) - opts.keep_after - cursor;
- Cell *first_cell = chain[cursor];
- IdString q_port = opts.ffcells.at(first_cell->type).second;
- dict<int, SigBit> taps_dict;
+ if (opts.maxlen > 0)
+ depth = std::min(opts.maxlen, depth);
- if (opts.tech)
- {
- vector<SigBit> qbits;
- vector<int> taps;
+ Cell *first_cell = chain[cursor];
+ IdString q_port = opts.ffcells.at(first_cell->type).second;
+ dict<int, SigBit> taps_dict;
- for (int i = 0; i < depth; i++)
- {
- Cell *cell = chain[cursor+i];
- auto qbit = sigmap(cell->getPort(q_port));
- qbits.push_back(qbit);
+ if (opts.tech)
+ {
+ vector<SigBit> qbits;
+ vector<int> taps;
- if (sigbit_with_non_chain_users.count(qbit))
- taps.push_back(i);
- }
+ for (int i = 0; i < depth; i++)
+ {
+ Cell *cell = chain[cursor+i];
+ auto qbit = sigmap(cell->getPort(q_port));
+ qbits.push_back(qbit);
- while (depth > 0)
- {
- if (taps.empty() || taps.back() < depth-1)
- taps.push_back(depth-1);
+ if (sigbit_with_non_chain_users.count(qbit))
+ taps.push_back(i);
+ }
- if (opts.tech->analyze(taps, qbits))
- break;
+ while (depth > 0)
+ {
+ if (taps.empty() || taps.back() < depth-1)
+ taps.push_back(depth-1);
- taps.pop_back();
- depth--;
- }
+ if (opts.tech->analyze(taps, qbits))
+ break;
- depth = 0;
- for (auto tap : taps) {
- taps_dict[tap] = qbits.at(tap);
- log_assert(depth < tap+1);
- depth = tap+1;
- }
- }
-
- if (depth < 2) {
- cursor++;
- continue;
- }
-
- Cell *last_cell = chain[cursor+depth-1];
-
- log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
- log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
-
- dff_count += depth;
- shreg_count += 1;
-
- string shreg_cell_type_str = "$__SHREG";
- if (opts.params) {
- shreg_cell_type_str += "_";
- } else {
- if (first_cell->type[1] != '_')
- shreg_cell_type_str += "_";
- shreg_cell_type_str += first_cell->type.substr(1);
- }
-
- if (opts.init) {
- vector<State> initval;
- for (int i = depth-1; i >= 0; i--) {
- SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
- if (sigbit_init.count(bit) == 0)
- initval.push_back(State::Sx);
- else if (sigbit_init.at(bit))
- initval.push_back(State::S1);
- else
- initval.push_back(State::S0);
- remove_init.insert(bit);
- }
- first_cell->setParam("\\INIT", initval);
- }
+ taps.pop_back();
+ depth--;
+ }
- if (opts.zinit)
- for (int i = depth-1; i >= 0; i--) {
- SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
- remove_init.insert(bit);
- }
+ depth = 0;
+ for (auto tap : taps) {
+ taps_dict[tap] = qbits.at(tap);
+ log_assert(depth < tap+1);
+ depth = tap+1;
+ }
+ }
- if (opts.params)
- {
- int param_clkpol = -1;
- int param_enpol = 2;
+ if (depth < 2) {
+ cursor++;
+ continue;
+ }
- if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
- if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
+ Cell *last_cell = chain[cursor+depth-1];
- if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
- if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
- if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
- if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
+ log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
+ log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
- log_assert(param_clkpol >= 0);
- first_cell->setParam("\\CLKPOL", param_clkpol);
- if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol);
- }
+ dff_count += depth;
+ shreg_count += 1;
- first_cell->type = shreg_cell_type_str;
- first_cell->setPort(q_port, last_cell->getPort(q_port));
- first_cell->setParam("\\DEPTH", depth);
+ string shreg_cell_type_str = "$__SHREG";
+ if (opts.params) {
+ shreg_cell_type_str += "_";
+ } else {
+ if (first_cell->type[1] != '_')
+ shreg_cell_type_str += "_";
+ shreg_cell_type_str += first_cell->type.substr(1);
+ }
- if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
- remove_cells.insert(first_cell);
+ if (opts.init) {
+ vector<State> initval;
+ for (int i = depth-1; i >= 0; i--) {
+ SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
+ if (sigbit_init.count(bit) == 0)
+ initval.push_back(State::Sx);
+ else if (sigbit_init.at(bit))
+ initval.push_back(State::S1);
+ else
+ initval.push_back(State::S0);
+ remove_init.insert(bit);
+ }
+ first_cell->setParam("\\INIT", initval);
+ }
- for (int i = 1; i < depth; i++)
- remove_cells.insert(chain[cursor+i]);
- cursor += depth;
- }
- }
+ if (opts.zinit)
+ for (int i = depth-1; i >= 0; i--) {
+ SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
+ remove_init.insert(bit);
+ }
- void cleanup()
- {
- for (auto cell : remove_cells)
- module->remove(cell);
+ if (opts.params)
+ {
+ int param_clkpol = -1;
+ int param_enpol = 2;
- for (auto wire : module->wires())
- {
- if (wire->attributes.count("\\init") == 0)
- continue;
+ if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
+ if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
+
+ if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
+ if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
+ if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
+ if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
- SigSpec initsig = sigmap(wire);
- Const &initval = wire->attributes.at("\\init");
+ log_assert(param_clkpol >= 0);
+ first_cell->setParam("\\CLKPOL", param_clkpol);
+ if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol);
+ }
+
+ first_cell->type = shreg_cell_type_str;
+ first_cell->setPort(q_port, last_cell->getPort(q_port));
+ first_cell->setParam("\\DEPTH", depth);
- for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
- if (remove_init.count(initsig[i]))
- initval[i] = State::Sx;
+ if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
+ remove_cells.insert(first_cell);
- if (SigSpec(initval).is_fully_undef())
- wire->attributes.erase("\\init");
+ for (int i = 1; i < depth; i++)
+ remove_cells.insert(chain[cursor+i]);
+ cursor += depth;
+ }
}
- remove_cells.clear();
- sigbit_chain_next.clear();
- sigbit_chain_prev.clear();
- chain_start_cells.clear();
- }
+ void cleanup()
+ {
+ for (auto cell : remove_cells)
+ module->remove(cell);
+
+ for (auto wire : module->wires())
+ {
+ if (wire->attributes.count("\\init") == 0)
+ continue;
- ShregmapWorker(Module *module, const ShregmapOptions &opts) :
- module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
- {
- if (opts.tech)
- opts.tech->init(module, sigmap);
+ SigSpec initsig = sigmap(wire);
+ Const &initval = wire->attributes.at("\\init");
- make_sigbit_chain_next_prev();
- find_chain_start_cells();
+ for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
+ if (remove_init.count(initsig[i]))
+ initval[i] = State::Sx;
- for (auto c : chain_start_cells) {
- vector<Cell*> chain = create_chain(c);
- process_chain(chain);
+ if (SigSpec(initval).is_fully_undef())
+ wire->attributes.erase("\\init");
+ }
+
+ remove_cells.clear();
+ sigbit_chain_next.clear();
+ sigbit_chain_prev.clear();
+ chain_start_cells.clear();
}
- cleanup();
- }
+ ShregmapWorker(Module *module, const ShregmapOptions &opts) :
+ module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
+ {
+ if (opts.tech)
+ opts.tech->init(module, sigmap);
+
+ make_sigbit_chain_next_prev();
+ find_chain_start_cells();
+
+ for (auto c : chain_start_cells) {
+ vector<Cell*> chain = create_chain(c);
+ process_chain(chain);
+ }
+
+ cleanup();
+ }
};
struct ShregmapPass : public Pass {
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