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enabled debug printing of MSR
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 23 Dec 2021 16:24:56 +0000
(16:24 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 23 Dec 2021 16:24:56 +0000
(16:24 +0000)
sim.py
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diff --git
a/sim.py
b/sim.py
index accac4fabc3196f3f39c0c1f3caf396953f69a69..c4d1b9d257fae4ce3bbf70e827816132e6a567d5 100755
(executable)
--- a/
sim.py
+++ b/
sim.py
@@
-304,9
+304,9
@@
class LibreSoCSim(SoCSDRAM):
If(dbg_addr == 0b10, # PC
pc.eq(dbg_dout), # capture PC
),
-
#
If(dbg_addr == 0b11, # MSR
-
#
Display(" msr: %016x", dbg_dout),
-
#
),
+ If(dbg_addr == 0b11, # MSR
+ Display(" msr: %016x", dbg_dout),
+ ),
If(dbg_addr == 0b1000, # CR
Display(" cr : %016x", dbg_dout),
),