ac: add cpdma_prefetch_writes_memory to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 6c91a5bd84845a6622a5ee0d2c0b9917ba42f025..b56460f8b3216a44fc239bdc3e9fc8897ff13ce2 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -465,6 +465,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                                     (info->chip_class >= GFX8 &&
                                      info->me_fw_feature >= 41);
 
+       info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
+
        /* Get the number of good compute units. */
        info->num_good_compute_units = 0;
        for (i = 0; i < info->max_se; i++)

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index ea6b911110807d39fc50968f6cbfb1c0452e0fa6..a1d4d142493e67ce624fcde75a25db63a5997f04 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -64,6 +64,7 @@ struct radeon_info {
        bool                        has_rbplus; /* if RB+ registers exist */
        bool                        has_load_ctx_reg_pkt;
        bool                        has_out_of_order_rast;
+       bool                        cpdma_prefetch_writes_memory;
 
        /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
        /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 5406ec72239c05c45a830787029e1e8c9e92c417..9786b4704ee591dde5eda787f8629d5b8f8b8bb8 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -363,8 +363,6 @@ radv_physical_device_init(struct radv_physical_device *device,
                                         device->rad_info.family == CHIP_RENOIR;
        }
 
-       device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
-
        /* Vega10/Raven need a special workaround for a hardware bug. */
        device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
                                  device->rad_info.family == CHIP_RAVEN;

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 380e2a8e632f7bbc3058438fc2de29699973e665..abbfa8d8c3fa9f002282330b910bd38df33bd2d7 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -281,7 +281,6 @@ struct radv_physical_device {
        struct wsi_device                       wsi_device;
 
        bool rbplus_allowed; /* if RB+ is allowed */
-       bool cpdma_prefetch_writes_memory;
        bool has_scissor_bug;
        bool has_tc_compat_zrange_bug;
 

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index f7ef20e89b0243946a8a9ba82b48369bfce77b08..c0e122a6ba7902fbbc80e9ebc66f1ee0109f7f5e 100644 (file)
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -631,7 +631,7 @@ radv_alloc_shader_memory(struct radv_device *device,
        slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
                                             RADEON_DOMAIN_VRAM,
                                             RADEON_FLAG_NO_INTERPROCESS_SHARING |
-                                            (device->physical_device->cpdma_prefetch_writes_memory ?
+                                            (device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
                                                     0 : RADEON_FLAG_READ_ONLY),
                                             RADV_BO_PRIORITY_SHADER);
        slab->ptr = (char*)device->ws->buffer_map(slab->bo);

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 49fb3cac951d9f4bbc62357e5d9e2cde56477e28..5082dfda438da25f011b9e7eca6df843e7406797 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1192,8 +1192,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
        sscreen->dcc_msaa_allowed =
                !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
 
-       sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= GFX8;
-
        (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
        sscreen->use_monolithic_shaders =
                (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index f9371f97a96264f3c34c71f20dc175729ebf8074..390b37e75b355e9540fd7a7d6d21d8cd3f6550e0 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -514,7 +514,6 @@ struct si_screen {
        bool                            record_llvm_ir;
        bool                            rbplus_allowed; /* if RB+ is allowed */
        bool                            dcc_msaa_allowed;
-       bool                            cpdma_prefetch_writes_memory;
 
        struct slab_parent_pool         pool_transfers;
 

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 9492fb7deef3189d04aa4bcb767f19d321178a3c..b8609e49fe16cc7541e9c6fdf27147da46af4da0 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5307,7 +5307,7 @@ bool si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader
 
        si_resource_reference(&shader->bo, NULL);
        shader->bo = si_aligned_buffer_create(&sscreen->b,
-                                             sscreen->cpdma_prefetch_writes_memory ?
+                                             sscreen->info.cpdma_prefetch_writes_memory ?
                                                0 : SI_RESOURCE_FLAG_READ_ONLY,
                                               PIPE_USAGE_IMMUTABLE,
                                               align(binary.rx_size, SI_CPDMA_ALIGNMENT),

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 07f8318d94a4670c162227c5567d18c71536f271..75d41ef4f567918a3f5e4b59685814274f9e9109 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -588,6 +588,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
     ws->info.max_alignment = 1024*1024;
     ws->info.has_graphics = true;
+    ws->info.cpdma_prefetch_writes_memory = true;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;