back.rtlil: Generate $anyconst and $anyseq cells.

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 8982f23ad410dd5a9329e25bf59b06b528503671..2f0ed6cd29d2ab2a8d13330b2ae22eb8f0f0f067 100644 (file)
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -370,6 +370,26 @@ class _RHSValueCompiler(_ValueCompiler):
             value_twos_compl = value.value & ((1 << value.nbits) - 1)
             return "{}'{:0{}b}".format(value.nbits, value_twos_compl, value.nbits)
 
+    def on_AnyConst(self, value):
+        res_bits, res_sign = value.shape()
+        res = self.s.rtlil.wire(width=res_bits)
+        self.s.rtlil.cell("$anyconst", ports={
+            "\\Y": res,
+        }, params={
+            "Y_WIDTH": res_bits,
+        }, src=src(value.src_loc))
+        return res
+
+    def on_AnySeq(self, value):
+        res_bits, res_sign = value.shape()
+        res = self.s.rtlil.wire(width=res_bits)
+        self.s.rtlil.cell("$anyseq", ports={
+            "\\Y": res,
+        }, params={
+            "Y_WIDTH": res_bits,
+        }, src=src(value.src_loc))
+        return res
+
     def on_Signal(self, value):
         wire_curr, wire_next = self.s.resolve(value)
         return wire_curr
@@ -503,6 +523,12 @@ class _LHSValueCompiler(_ValueCompiler):
     def on_Const(self, value):
         raise TypeError # :nocov:
 
+    def on_AnyConst(self, value):
+        raise TypeError # :nocov:
+
+    def on_AnySeq(self, value):
+        raise TypeError # :nocov:
+
     def on_Operator(self, value):
         raise TypeError # :nocov: