nvc0: index buffers are back

Probably because long methods are gone index buffers must be
explicit again.

diff --git a/src/gallium/drivers/nvc0/nvc0_3d.xml.h b/src/gallium/drivers/nvc0/nvc0_3d.xml.h
index b727a8cb89537a0e9ad0e7dc12e29188ab4b9d00..b411e549f2ef3294e6481b2d0d9a858e47c41b93 100644 (file)
--- a/src/gallium/drivers/nvc0/nvc0_3d.xml.h
+++ b/src/gallium/drivers/nvc0/nvc0_3d.xml.h
@@ -8,13 +8,13 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
 git clone git://0x04.net/rules-ng-ng
 
 The rules-ng-ng source files this header was generated from are:
-- nvc0_3d.xml    (  26726 bytes, from 2010-10-22 00:29:01)
-- copyright.xml  (   6498 bytes, from 2010-09-30 18:32:24)
-- nv_defs.xml    (   4437 bytes, from 2010-07-24 13:13:40)
-- nv_3ddefs.xml  (  16394 bytes, from 2010-10-11 14:37:46)
-- nv_object.xml  (  11357 bytes, from 2010-10-19 20:33:50)
-- nvchipsets.xml (   2907 bytes, from 2010-10-12 17:28:45)
-- nv50_defs.xml  (   4482 bytes, from 2010-10-03 10:27:25)
+- nvc0_3d.xml    (  28058 bytes, from 2010-11-26 18:05:20)
+- copyright.xml  (   6452 bytes, from 2010-11-25 23:28:20)
+- nv_defs.xml    (   4437 bytes, from 2010-07-06 07:43:58)
+- nv_3ddefs.xml  (  16394 bytes, from 2010-10-09 08:27:14)
+- nv_object.xml  (  11547 bytes, from 2010-11-26 16:41:56)
+- nvchipsets.xml (   3074 bytes, from 2010-11-07 00:36:28)
+- nv50_defs.xml  (   4482 bytes, from 2010-10-03 13:18:37)
 
 Copyright (C) 2006-2010 by the following authors:
 - Artur Huillet <arthur.huillet@free.fr> (ahuillet)
@@ -27,7 +27,7 @@ Copyright (C) 2006-2010 by the following authors:
 - Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
 - EdB <edb_@users.sf.net> (edb_)
 - Erik Waling <erikwailing@users.sf.net> (erikwaling)
-- Francisco Jerez <currojerez@riseup.net> (curro, curro_, currojerez)
+- Francisco Jerez <currojerez@riseup.net> (curro)
 - imirkin <imirkin@users.sf.net> (imirkin)
 - jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
 - Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
@@ -338,6 +338,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define NVC0_3D_SCREEN_SCISSOR_VERT_Y__MASK                    0x0000ffff
 #define NVC0_3D_SCREEN_SCISSOR_VERT_Y__SHIFT                   0
 
+#define NVC0_3D_VERTEX_ID                                      0x00001118
+
 #define NVC0_3D_VTX_ATTR_DEFINE                                        0x0000114c
 #define NVC0_3D_VTX_ATTR_DEFINE_ATTR__MASK                     0x000000ff
 #define NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT                    0
@@ -716,6 +718,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define NVC0_3D_POLYGON_OFFSET_UNITS                           0x000015bc
 
 #define NVC0_3D_GP_BUILTIN_RESULT_EN                           0x000015cc
+#define NVC0_3D_GP_BUILTIN_RESULT_EN_LAYER                     0x00010000
 
 #define NVC0_3D_MULTISAMPLE_MODE                               0x000015d0
 #define NVC0_3D_MULTISAMPLE_MODE_1X                            0x00000000
@@ -765,6 +768,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define NVC0_3D_VERTEX_BASE_LOW                                        0x000015f8
 
 #define NVC0_3D_POINT_COORD_REPLACE                            0x00001604
+#define NVC0_3D_POINT_COORD_REPLACE_BITS__MASK                 0x00001fff
+#define NVC0_3D_POINT_COORD_REPLACE_BITS__SHIFT                        0
 
 #define NVC0_3D_CODE_ADDRESS_HIGH                              0x00001608
 
@@ -837,6 +842,20 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #define NVC0_3D_UNK17BC_LIMIT                                  0x000017c4
 
+#define NVC0_3D_INDEX_ARRAY_START_HIGH                         0x000017c8
+
+#define NVC0_3D_INDEX_ARRAY_START_LOW                          0x000017cc
+
+#define NVC0_3D_INDEX_ARRAY_LIMIT_HIGH                         0x000017d0
+
+#define NVC0_3D_INDEX_ARRAY_LIMIT_LOW                          0x000017d4
+
+#define NVC0_3D_INDEX_LOG2_SIZE                                        0x000017d8
+
+#define NVC0_3D_INDEX_BATCH_FIRST                              0x000017dc
+
+#define NVC0_3D_INDEX_BATCH_COUNT                              0x000017e0
+
 #define NVC0_3D_VERTEX_ARRAY_PER_INSTANCE(i0)                 (0x00001880 + 0x4*(i0))
 #define NVC0_3D_VERTEX_ARRAY_PER_INSTANCE__ESIZE               0x00000004
 #define NVC0_3D_VERTEX_ARRAY_PER_INSTANCE__LEN                 0x00000020
@@ -1019,17 +1038,30 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define NVC0_3D_CB_DATA__ESIZE                                 0x00000004
 #define NVC0_3D_CB_DATA__LEN                                   0x00000010
 
-#define NVC0_3D_BIND_TIC(i0)                                  (0x00002404 + 0x20*(i0))
-#define NVC0_3D_BIND_TIC__ESIZE                                        0x00000020
-#define NVC0_3D_BIND_TIC__LEN                                  0x00000005
-
 #define NVC0_3D_BIND_TSC(i0)                                  (0x00002400 + 0x20*(i0))
 #define NVC0_3D_BIND_TSC__ESIZE                                        0x00000020
 #define NVC0_3D_BIND_TSC__LEN                                  0x00000005
+#define NVC0_3D_BIND_TSC_ACTIVE                                        0x00000001
+#define NVC0_3D_BIND_TSC_SAMPLER__MASK                         0x00000ff0
+#define NVC0_3D_BIND_TSC_SAMPLER__SHIFT                                4
+#define NVC0_3D_BIND_TSC_TSC__MASK                             0x01fff000
+#define NVC0_3D_BIND_TSC_TSC__SHIFT                            12
+
+#define NVC0_3D_BIND_TIC(i0)                                  (0x00002404 + 0x20*(i0))
+#define NVC0_3D_BIND_TIC__ESIZE                                        0x00000020
+#define NVC0_3D_BIND_TIC__LEN                                  0x00000005
+#define NVC0_3D_BIND_TIC_ACTIVE                                        0x00000001
+#define NVC0_3D_BIND_TIC_TEXTURE__MASK                         0x000001fe
+#define NVC0_3D_BIND_TIC_TEXTURE__SHIFT                                1
+#define NVC0_3D_BIND_TIC_TIC__MASK                             0x7ffffe00
+#define NVC0_3D_BIND_TIC_TIC__SHIFT                            9
 
 #define NVC0_3D_CB_BIND(i0)                                   (0x00002410 + 0x20*(i0))
 #define NVC0_3D_CB_BIND__ESIZE                                 0x00000020
 #define NVC0_3D_CB_BIND__LEN                                   0x00000005
+#define NVC0_3D_CB_BIND_VALID                                  0x00000001
+#define NVC0_3D_CB_BIND_INDEX__MASK                            0x000000f0
+#define NVC0_3D_CB_BIND_INDEX__SHIFT                           4
 
 #define NVC0_3D_TFB_VARYING_LOCS(i0)                          (0x00002800 + 0x4*(i0))
 #define NVC0_3D_TFB_VARYING_LOCS__ESIZE                                0x00000004

diff --git a/src/gallium/drivers/nvc0/nvc0_context.h b/src/gallium/drivers/nvc0/nvc0_context.h
index 61a9b888786542a5d54fd32fdffd2ddf3746a7d3..d0f78a564d769ce09c014371cc528361f68bf571 100644 (file)
--- a/src/gallium/drivers/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nvc0/nvc0_context.h
@@ -73,6 +73,7 @@ struct nvc0_context {
    struct {
       uint32_t instance_bits;
       uint32_t instance_base;
+      int32_t index_bias;
       boolean prim_restart;
       uint8_t num_vtxbufs;
       uint8_t num_vtxelts;

diff --git a/src/gallium/drivers/nvc0/nvc0_vbo.c b/src/gallium/drivers/nvc0/nvc0_vbo.c
index 9fa1ad42ad30f6ba9424b6e63e5a52b6c8b43562..b8529e632d2ead27e75fed4926da3f4bc53de73b 100644 (file)
--- a/src/gallium/drivers/nvc0/nvc0_vbo.c
+++ b/src/gallium/drivers/nvc0/nvc0_vbo.c
@@ -131,7 +131,7 @@ nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
       ve = &vertex->element[i];
       vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index];
 
-      if (!nvc0_resource_mapped_by_gpu(vb->buffer) || 1)
+      if (!nvc0_resource_mapped_by_gpu(vb->buffer))
          nvc0->vbo_fifo |= 1 << i;
 
       if (1 || likely(vb->stride)) {
@@ -380,45 +380,79 @@ nvc0_draw_elements_inline_u32(struct nouveau_channel *chan, uint32_t *map,
 static void
 nvc0_draw_elements(struct nvc0_context *nvc0,
                    unsigned mode, unsigned start, unsigned count,
-                   unsigned instance_count,
-                   unsigned index_size, int index_bias)
+                   unsigned instance_count, int32_t index_bias)
 {
    struct nouveau_channel *chan = nvc0->screen->base.channel;
    void *data;
    struct pipe_transfer *transfer;
    unsigned prim;
+   unsigned index_size = nvc0->idxbuf.index_size;
 
    chan->flush_notify = nvc0_draw_vbo_flush_notify;
    chan->user_private = nvc0;
 
    prim = nvc0_prim_gl(mode);
 
-   data = pipe_buffer_map(&nvc0->pipe,
-                          nvc0->idxbuf.buffer, PIPE_TRANSFER_READ, &transfer);
-   if (!data)
-      return;
+   if (index_bias != nvc0->state.index_bias) {
+      BEGIN_RING(chan, RING_3D(VB_ELEMENT_BASE), 1);
+      OUT_RING  (chan, index_bias);
+      nvc0->state.index_bias = index_bias;
+   }
 
-   while (instance_count--) {
-      BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
-      OUT_RING  (chan, prim);
-      switch (index_size) {
-      case 1:
-         nvc0_draw_elements_inline_u08(chan, data, start, count);
-         break;
-      case 2:
-         nvc0_draw_elements_inline_u16(chan, data, start, count);
-         break;
-      case 4:
-         nvc0_draw_elements_inline_u32(chan, data, start, count);
-         break;
-      default:
-         assert(0);
-         return;
+   if (nvc0_resource_mapped_by_gpu(nvc0->idxbuf.buffer)) {
+      struct nouveau_bo *bo = nvc0_resource(nvc0->idxbuf.buffer)->bo;
+      unsigned offset = nvc0->idxbuf.offset;
+      unsigned limit = nvc0->idxbuf.buffer->width0 - 1;
+
+      if (index_size == 4)
+         index_size = 2;
+      else
+      if (index_size == 2)
+         index_size = 1;
+
+      while (instance_count--) {
+         MARK_RING (chan, 11, 4);
+         BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
+         OUT_RING  (chan, mode);
+         BEGIN_RING(chan, RING_3D(INDEX_ARRAY_START_HIGH), 7);
+         OUT_RELOCh(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART);
+         OUT_RELOCl(chan, bo, offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART);
+         OUT_RELOCh(chan, bo, limit, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART);
+         OUT_RELOCl(chan, bo, limit, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART);
+         OUT_RING  (chan, index_size);
+         OUT_RING  (chan, start);
+         OUT_RING  (chan, count);
+         INLIN_RING(chan, RING_3D(VERTEX_END_GL), 0);
+
+         mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
       }
-      BEGIN_RING(chan, RING_3D(VERTEX_END_GL), 1);
-      OUT_RING  (chan, 0);
+   } else {
+      data = pipe_buffer_map(&nvc0->pipe, nvc0->idxbuf.buffer,
+                             PIPE_TRANSFER_READ, &transfer);
+      if (!data)
+         return;
 
-      prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
+      while (instance_count--) {
+         BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
+         OUT_RING  (chan, prim);
+         switch (index_size) {
+         case 1:
+            nvc0_draw_elements_inline_u08(chan, data, start, count);
+            break;
+         case 2:
+            nvc0_draw_elements_inline_u16(chan, data, start, count);
+            break;
+         case 4:
+            nvc0_draw_elements_inline_u32(chan, data, start, count);
+            break;
+         default:
+            assert(0);
+            return;
+         }
+         INLIN_RING(chan, RING_3D(VERTEX_END_GL), 0);
+
+         prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
+      }
    }
 
    chan->flush_notify = NULL;
@@ -473,7 +507,6 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 
       nvc0_draw_elements(nvc0,
                          info->mode, info->start, info->count,
-                         info->instance_count,
-                         nvc0->idxbuf.index_size, info->index_bias);
+                         info->instance_count, info->index_bias);
    }
 }