ac/gpu_info: add has_eqaa_surface_allocator
authorMarek Olšák <marek.olsak@amd.com>
Wed, 2 May 2018 22:59:54 +0000 (18:59 -0400)
committerMarek Olšák <marek.olsak@amd.com>
Thu, 10 May 2018 22:39:58 +0000 (18:39 -0400)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/amd/common/ac_gpu_info.c
src/amd/common/ac_gpu_info.h
src/gallium/drivers/radeonsi/si_pipe.c
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

index 7678a18b355d0d3fd79aba9ec14268e56d290c37..f05dd77a21ef1f2097911cc9ed8440bcbef7ba34 100644 (file)
@@ -322,6 +322,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
        info->has_bo_metadata = true;
        info->has_gpu_reset_status_query = true;
        info->has_gpu_reset_counter_query = false;
+       info->has_eqaa_surface_allocator = true;
 
        info->num_render_backends = amdinfo->rb_pipes;
        /* The value returned by the kernel driver was wrong. */
@@ -460,7 +461,7 @@ void ac_print_gpu_info(struct radeon_info *info)
        printf("    vce_fw_version = %u\n", info->vce_fw_version);
        printf("    vce_harvest_config = %i\n", info->vce_harvest_config);
 
-       printf("Kernel info:\n");
+       printf("Kernel & winsys capabilities:\n");
        printf("    drm = %i.%i.%i\n", info->drm_major,
               info->drm_minor, info->drm_patchlevel);
        printf("    has_userptr = %i\n", info->has_userptr);
@@ -475,6 +476,7 @@ void ac_print_gpu_info(struct radeon_info *info)
        printf("    has_bo_metadata = %u\n", info->has_bo_metadata);
        printf("    has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
        printf("    has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
+       printf("    has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
 
        printf("Shader core info:\n");
        printf("    max_shader_clock = %i\n", info->max_shader_clock);
index f5b74579ef19fc20cdc9d8092b93159c0fa851c7..f8e4adf0d41f61b5eb7d50d5048bafdb45f1702c 100644 (file)
@@ -86,7 +86,7 @@ struct radeon_info {
        uint32_t                    vce_fw_version;
        uint32_t                    vce_harvest_config;
 
-       /* Kernel info. */
+       /* Kernel & winsys capabilities. */
        uint32_t                    drm_major; /* version */
        uint32_t                    drm_minor;
        uint32_t                    drm_patchlevel;
@@ -102,6 +102,7 @@ struct radeon_info {
        bool                        has_bo_metadata;
        bool                        has_gpu_reset_status_query;
        bool                        has_gpu_reset_counter_query;
+       bool                        has_eqaa_surface_allocator;
 
        /* Shader cores. */
        uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
index bf61b0071e75ebe465dffcc2ecb48c4ceaae7f0d..fe0a20ba6cd1e0d307f87c713159e11b0dbd11b2 100644 (file)
@@ -1082,7 +1082,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
         *
         * Only MSAA color and depth buffers are overriden.
         */
-       if (sscreen->info.drm_major == 3) {
+       if (sscreen->info.has_eqaa_surface_allocator) {
                const char *eqaa = debug_get_option("EQAA", NULL);
                unsigned s,z,f;
 
index 7189b61ef11738d81250b349f7186ef846cf8153..1eecb23d9dd0229fe36617e254805b60b3727ab2 100644 (file)
@@ -536,6 +536,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.has_bo_metadata = false;
     ws->info.has_gpu_reset_status_query = false;
     ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
+    ws->info.has_eqaa_surface_allocator = false;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;