intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF

diff --git a/techlibs/intel_alm/common/abc9_model.v b/techlibs/intel_alm/common/abc9_model.v
index 8ad52e13ac01d0298060c9711b3381b1ef4325d9..8f06d38353bf07f86da7b09beaa415ec402730cc 100644 (file)
--- a/techlibs/intel_alm/common/abc9_model.v
+++ b/techlibs/intel_alm/common/abc9_model.v
@@ -1,21 +1,3 @@
-`ifdef cyclonev
-`define SYNCPATH 262
-`define SYNCSETUP 522
-`define COMBPATH 0
-`endif
-`ifdef cyclone10gx
-`define SYNCPATH 219
-`define SYNCSETUP 268
-`define COMBPATH 0
-`endif
-
-// fallback for when a family isn't detected (e.g. when techmapping for equivalence)
-`ifndef SYNCPATH
-`define SYNCPATH 0
-`define SYNCSETUP 0
-`define COMBPATH 0
-`endif
-
 // This is a purely-synchronous flop, that ABC9 can use for sequential synthesis.
 (* abc9_flop, lib_whitebox *)
 module $__MISTRAL_FF_SYNCONLY (
@@ -23,33 +5,6 @@ module $__MISTRAL_FF_SYNCONLY (
     output reg Q
 );
 
-specify
-    if (ENA) (posedge CLK => (Q : DATAIN)) = `SYNCPATH;
-    if (ENA) (posedge CLK => (Q : SCLR)) = `SYNCPATH;
-    if (ENA) (posedge CLK => (Q : SLOAD)) = `SYNCPATH;
-    if (ENA) (posedge CLK => (Q : SDATA)) = `SYNCPATH;
-
-    $setup(DATAIN, posedge CLK, `SYNCSETUP);
-    $setup(ENA, posedge CLK, `SYNCSETUP);
-    $setup(SCLR, posedge CLK, `SYNCSETUP);
-    $setup(SLOAD, posedge CLK, `SYNCSETUP);
-    $setup(SDATA, posedge CLK, `SYNCSETUP);
-endspecify
-
-initial begin
-    // Altera flops initialise to zero.
-       Q = 0;
-end
-
-always @(posedge CLK) begin
-    // Clock-enable
-       if (ENA) begin
-        // Synchronous clear
-        if (SCLR) Q <= 0;
-        // Synchronous load
-        else if (SLOAD) Q <= SDATA;
-        else Q <= DATAIN;
-    end
-end
+MISTRAL_FF ff (.DATAIN(DATAIN), .CLK(CLK), .ENA(ENA), .ACLR(1'b1), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q));
 
 endmodule

diff --git a/techlibs/intel_alm/common/dff_sim.v b/techlibs/intel_alm/common/dff_sim.v
index 94aa37fb56bb5c0d79f237e656abcc4ec7eb38b5..38e3d661837f8c3810328d422cbd170154e315b1 100644 (file)
--- a/techlibs/intel_alm/common/dff_sim.v
+++ b/techlibs/intel_alm/common/dff_sim.v
@@ -90,7 +90,7 @@ specify
     $setup(SLOAD, posedge CLK, `SYNCSETUP);
     $setup(SDATA, posedge CLK, `SYNCSETUP);
 
-    (ACLR => Q) = `COMBPATH;
+    if (!ACLR) (ACLR => Q) = `COMBPATH;
 endspecify
 
 initial begin