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diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 980e42a77529a68193981e3a5fd1cd12a3a5118e..7f9875991b7d64c4476a03e606b7fae054378f49 100644 (file)
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -40,9 +40,9 @@ Now lets review all of the relevant material on this page before we begin the wi
 
 Next we will wire up the STLINKv2 and our FPGA in three separate stages. 
 
-* First we will attach the FEMALE end of a FEMALE-TO-MALE (FTM) jumper cable to each necessary header pin on the STLINKv2. 
+* First we will attach the FEMALE end of a ***FEMALE-TO-MALE (FTM)*** jumper cable to each necessary header pin on the STLINKv2. 
 
-* Then we will attach one end of a FEMALE-TO-FEMALE (FTF) cable to each male header pin on the FPGA.
+* Then we will attach one end of a ***FEMALE-TO-FEMALE (FTF)*** cable to each male header pin on the FPGA.
 
 * Finally, we will connect the wires from the STLINKv2 to the wires from the FPGA by matching the colours of the wires.