std::stringstream sstr;
sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
- RTLIL::Cell *cell = new RTLIL::Cell;
+ RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
- cell->name = sstr.str();
- cell->type = type;
- current_module->cells[cell->name] = cell;
- RTLIL::Wire *wire = new RTLIL::Wire;
+ RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", result_width);
wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
- wire->name = cell->name + "_Y";
- wire->width = result_width;
- current_module->wires[wire->name] = wire;
if (gen_attributes)
for (auto &attr : that->attributes) {
std::stringstream sstr;
sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
- RTLIL::Cell *cell = new RTLIL::Cell;
+ RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype);
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
- cell->name = sstr.str();
- cell->type = celltype;
- current_module->cells[cell->name] = cell;
- RTLIL::Wire *wire = new RTLIL::Wire;
+ RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", width);
wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
- wire->name = cell->name + "_Y";
- wire->width = width;
- current_module->wires[wire->name] = wire;
if (that != NULL)
for (auto &attr : that->attributes) {
std::stringstream sstr;
sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
- RTLIL::Cell *cell = new RTLIL::Cell;
+ RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
- cell->name = sstr.str();
- cell->type = type;
- current_module->cells[cell->name] = cell;
- RTLIL::Wire *wire = new RTLIL::Wire;
+ RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", result_width);
wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
- wire->name = cell->name + "_Y";
- wire->width = result_width;
- current_module->wires[wire->name] = wire;
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
std::stringstream sstr;
sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
- RTLIL::Cell *cell = new RTLIL::Cell;
+ RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
- cell->name = sstr.str();
- cell->type = "$mux";
- current_module->cells[cell->name] = cell;
- RTLIL::Wire *wire = new RTLIL::Wire;
+ RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", left.size());
wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
- wire->name = cell->name + "_Y";
- wire->width = left.size();
- current_module->wires[wire->name] = wire;
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
std::stringstream sstr;
sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
- RTLIL::Cell *cell = new RTLIL::Cell;
+ RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
- cell->name = sstr.str();
- cell->type = "$memrd";
- current_module->cells[cell->name] = cell;
- RTLIL::Wire *wire = new RTLIL::Wire;
+ RTLIL::Wire *wire = current_module->addWire(cell->name + "_DATA", current_module->memories[str]->width);
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
- wire->name = cell->name + "_DATA";
- wire->width = current_module->memories[str]->width;
- current_module->wires[wire->name] = wire;
int addr_bits = 1;
while ((1 << addr_bits) < current_module->memories[str]->size)
std::stringstream sstr;
sstr << "$memwr$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
- RTLIL::Cell *cell = new RTLIL::Cell;
+ RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memwr");
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
- cell->name = sstr.str();
- cell->type = "$memwr";
- current_module->cells[cell->name] = cell;
int addr_bits = 1;
while ((1 << addr_bits) < current_module->memories[str]->size)
std::stringstream sstr;
sstr << "$assert$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
- RTLIL::Cell *cell = new RTLIL::Cell;
+ RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$assert");
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
- cell->name = sstr.str();
- cell->type = "$assert";
- current_module->cells[cell->name] = cell;
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
case AST_CELL:
{
int port_counter = 0, para_counter = 0;
- RTLIL::Cell *cell = new RTLIL::Cell;
+
+ if (current_module->count_id(str) != 0)
+ log_error("Re-definition of cell `%s' at %s:%d!\n",
+ str.c_str(), filename.c_str(), linenum);
+
+ RTLIL::Cell *cell = current_module->addCell(str, "");
cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
- cell->name = str;
+
for (auto it = children.begin(); it != children.end(); it++) {
AstNode *child = *it;
if (child->type == AST_CELLTYPE) {
attr.first.c_str(), filename.c_str(), linenum);
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- if (current_module->cells.count(cell->name) != 0)
- log_error("Re-definition of cell `%s' at %s:%d!\n",
- str.c_str(), filename.c_str(), linenum);
- current_module->cells[str] = cell;
}
break;
TOK_CELL TOK_ID TOK_ID EOL {
if (current_module->cells.count($3) != 0)
rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell %s.", $3).c_str());
- current_cell = new RTLIL::Cell;
- current_cell->type = $2;
- current_cell->name = $3;
+ current_cell = current_module->addCell($3, $2);
current_cell->attributes = attrbuf;
- current_module->cells[$3] = current_cell;
attrbuf.clear();
free($2);
free($3);
static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
{
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$_INV_";
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
cell->connections["\\A"] = A;
cell->connections["\\Y"] = module->addWire(NEW_ID);
- module->add(cell);
return cell->connections["\\Y"];
}
static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$_XOR_";
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$_XOR_");
cell->connections["\\A"] = A;
cell->connections["\\B"] = B;
cell->connections["\\Y"] = module->addWire(NEW_ID);
- module->add(cell);
return cell->connections["\\Y"];
}
static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$_AND_";
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$_AND_");
cell->connections["\\A"] = A;
cell->connections["\\B"] = B;
cell->connections["\\Y"] = module->addWire(NEW_ID);
- module->add(cell);
return cell->connections["\\Y"];
}
static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$_OR_";
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$_OR_");
cell->connections["\\A"] = A;
cell->connections["\\B"] = B;
cell->connections["\\Y"] = module->addWire(NEW_ID);
- module->add(cell);
return cell->connections["\\Y"];
}
}
}
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$_INV_";
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
cell->connections["\\A"] = iq_sig;
cell->connections["\\Y"] = iqn_sig;
- module->add(cell);
- cell = new RTLIL::Cell;
- cell->name = NEW_ID;
+ cell = module->addCell(NEW_ID, "");
cell->connections["\\D"] = data_sig;
cell->connections["\\Q"] = iq_sig;
cell->connections["\\C"] = clk_sig;
- module->add(cell);
if (clear_sig.size() == 0 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
}
}
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$_INV_";
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$_INV_");
cell->connections["\\A"] = iq_sig;
cell->connections["\\Y"] = iqn_sig;
- module->add(cell);
if (clear_sig.size() == 1)
{
if (clear_polarity == true || clear_polarity != enable_polarity)
{
- RTLIL::Cell *inv = new RTLIL::Cell;
- inv->name = NEW_ID;
- inv->type = "$_INV_";
+ RTLIL::Cell *inv = module->addCell(NEW_ID, "$_INV_");
inv->connections["\\A"] = clear_sig;
inv->connections["\\Y"] = module->addWire(NEW_ID);
- module->add(inv);
if (clear_polarity == true)
clear_negative = inv->connections["\\Y"];
clear_enable = inv->connections["\\Y"];
}
- RTLIL::Cell *data_gate = new RTLIL::Cell;
- data_gate->name = NEW_ID;
- data_gate->type = "$_AND_";
+ RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_AND_");
data_gate->connections["\\A"] = data_sig;
data_gate->connections["\\B"] = clear_negative;
data_gate->connections["\\Y"] = data_sig = module->addWire(NEW_ID);
- module->add(data_gate);
- RTLIL::Cell *enable_gate = new RTLIL::Cell;
- enable_gate->name = NEW_ID;
- enable_gate->type = enable_polarity ? "$_OR_" : "$_AND_";
+ RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
enable_gate->connections["\\A"] = enable_sig;
enable_gate->connections["\\B"] = clear_enable;
enable_gate->connections["\\Y"] = data_sig = module->addWire(NEW_ID);
- module->add(enable_gate);
}
if (preset_sig.size() == 1)
if (preset_polarity == false || preset_polarity != enable_polarity)
{
- RTLIL::Cell *inv = new RTLIL::Cell;
- inv->name = NEW_ID;
- inv->type = "$_INV_";
+ RTLIL::Cell *inv = module->addCell(NEW_ID, "$_INV_");
inv->connections["\\A"] = preset_sig;
inv->connections["\\Y"] = module->addWire(NEW_ID);
- module->add(inv);
if (preset_polarity == false)
preset_positive = inv->connections["\\Y"];
preset_enable = inv->connections["\\Y"];
}
- RTLIL::Cell *data_gate = new RTLIL::Cell;
- data_gate->name = NEW_ID;
- data_gate->type = "$_OR_";
+ RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_OR_");
data_gate->connections["\\A"] = data_sig;
data_gate->connections["\\B"] = preset_positive;
data_gate->connections["\\Y"] = data_sig = module->addWire(NEW_ID);
- module->add(data_gate);
- RTLIL::Cell *enable_gate = new RTLIL::Cell;
- enable_gate->name = NEW_ID;
- enable_gate->type = enable_polarity ? "$_OR_" : "$_AND_";
+ RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_");
enable_gate->connections["\\A"] = enable_sig;
enable_gate->connections["\\B"] = preset_enable;
enable_gate->connections["\\Y"] = data_sig = module->addWire(NEW_ID);
- module->add(enable_gate);
}
- cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N');
+ cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
cell->connections["\\D"] = data_sig;
cell->connections["\\Q"] = iq_sig;
cell->connections["\\E"] = enable_sig;
- module->add(cell);
}
struct LibertyFrontend : public Frontend {
for (auto &it : memories)
new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
- for (auto &it : cells)
- new_mod->cells[it.first] = new RTLIL::Cell(*it.second);
+ for (auto &it : cells) {
+ new_mod->cells[it.first] = new RTLIL::Cell;
+ new_mod->cells[it.first]->name = it.second->name;
+ new_mod->cells[it.first]->type = it.second->type;
+ new_mod->cells[it.first]->connections = it.second->connections;
+ new_mod->cells[it.first]->parameters = it.second->parameters;
+ new_mod->cells[it.first]->attributes = it.second->attributes;
+ }
for (auto &it : processes)
new_mod->processes[it.first] = it.second->clone();
delete cell;
}
+void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
+{
+ assert(wires[wire->name] == wire);
+ wires.erase(wire->name);
+ wire->name = new_name;
+ add(wire);
+}
+
+void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
+{
+ assert(cells[cell->name] == cell);
+ cells.erase(cell->name);
+ cell->name = new_name;
+ add(cell);
+}
+
+void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
+{
+ assert(count_id(old_name) != 0);
+ if (wires.count(old_name))
+ rename(wires.at(old_name), new_name);
+ else if (cells.count(old_name))
+ rename(cells.at(old_name), new_name);
+ else
+ log_abort();
+}
+
static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
{
if (a->port_id && !b->port_id)
return attributes.at(id).as_bool(); \
}
-struct RTLIL::Module {
+struct RTLIL::Module
+{
RTLIL::IdString name;
std::set<RTLIL::IdString> avail_parameters;
std::map<RTLIL::IdString, RTLIL::Wire*> wires;
void add(RTLIL::Cell *cell);
void remove(RTLIL::Cell *cell);
+ void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
+ void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);
+ void rename(RTLIL::IdString old_name, RTLIL::IdString new_name);
+
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
Memory();
};
-struct RTLIL::Cell {
+struct RTLIL::Cell
+{
+protected:
+ // Use module->addCell() and module->remove() to create or destroy modules.
+ friend struct RTLIL::Module;
+ Cell() { };
+ ~Cell() { };
+
+public:
+ // do not copy simply cells
+ Cell(RTLIL::Cell &other) = delete;
+ void operator=(RTLIL::Cell &other) = delete;
+
RTLIL::IdString name;
RTLIL::IdString type;
std::map<RTLIL::IdString, RTLIL::SigSpec> connections;
map_signal(sig_q, 'f', map_signal(sig_d));
- module->cells.erase(cell->name);
- delete cell;
+ module->remove(cell);
return;
}
map_signal(sig_y, 'n', map_signal(sig_a));
- module->cells.erase(cell->name);
- delete cell;
+ module->remove(cell);
return;
}
else
log_abort();
- module->cells.erase(cell->name);
- delete cell;
+ module->remove(cell);
return;
}
map_signal(sig_y, 'm', mapped_a, mapped_b, mapped_s);
- module->cells.erase(cell->name);
- delete cell;
+ module->remove(cell);
return;
}
}
continue;
}
if (c->type == "\\INV") {
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->type = "$_INV_";
- cell->name = remap_name(c->name);
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_INV_");
cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]);
cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]);
- module->cells[cell->name] = cell;
design->select(module, cell);
continue;
}
if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR") {
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->type = "$_" + c->type.substr(1) + "_";
- cell->name = remap_name(c->name);
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]);
cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].as_wire()->name)]);
cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]);
- module->cells[cell->name] = cell;
design->select(module, cell);
continue;
}
if (c->type == "\\MUX") {
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->type = "$_MUX_";
- cell->name = remap_name(c->name);
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
cell->connections["\\A"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\A"].as_wire()->name)]);
cell->connections["\\B"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\B"].as_wire()->name)]);
cell->connections["\\S"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\S"].as_wire()->name)]);
cell->connections["\\Y"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Y"].as_wire()->name)]);
- module->cells[cell->name] = cell;
design->select(module, cell);
continue;
}
if (c->type == "\\DFF") {
log_assert(clk_sig.size() == 1);
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_";
- cell->name = remap_name(c->name);
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].as_wire()->name)]);
cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].as_wire()->name)]);
cell->connections["\\C"] = clk_sig;
- module->cells[cell->name] = cell;
design->select(module, cell);
continue;
}
}
if (c->type == "\\_dff_") {
log_assert(clk_sig.size() == 1);
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->type = clk_polarity ? "$_DFF_P_" : "$_DFF_N_";
- cell->name = remap_name(c->name);
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
cell->connections["\\D"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\D"].as_wire()->name)]);
cell->connections["\\Q"] = RTLIL::SigSpec(module->wires[remap_name(c->connections["\\Q"].as_wire()->name)]);
cell->connections["\\C"] = clk_sig;
- module->cells[cell->name] = cell;
design->select(module, cell);
continue;
}
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->type = c->type;
+ RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
cell->parameters = c->parameters;
- cell->name = remap_name(c->name);
for (auto &conn : c->connections) {
RTLIL::SigSpec newsig;
for (auto &c : conn.second.chunks()) {
}
cell->connections[conn.first] = newsig;
}
- module->cells[cell->name] = cell;
design->select(module, cell);
}
}
module->add(wire);
}
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = dff_name;
+ RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name);
cell->connections["\\D"] = module->wires.at(RTLIL::escape_id(d));
cell->connections["\\Q"] = module->wires.at(RTLIL::escape_id(q));
- module->add(cell);
continue;
}
if (!strcmp(cmd, ".gate"))
{
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- module->add(cell);
-
char *p = strtok(NULL, " \t\r\n");
if (p == NULL)
goto error;
- cell->type = RTLIL::escape_id(p);
+
+ RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(p));
while ((p = strtok(NULL, " \t\r\n")) != NULL) {
char *q = strchr(p, '=');
if (q == NULL || !q[0] || !q[1])
goto error;
*(q++) = 0;
- if (module->wires.count(RTLIL::escape_id(q)) == 0) {
- RTLIL::Wire *wire = new RTLIL::Wire;
- wire->name = RTLIL::escape_id(q);
- module->add(wire);
- }
+ if (module->wires.count(RTLIL::escape_id(q)) == 0)
+ module->addWire(RTLIL::escape_id(q));
cell->connections[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q));
}
continue;
goto continue_without_read;
}
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$lut";
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
cell->connections["\\I"] = input_sig;
cell->connections["\\O"] = output_sig;
lutptr = &cell->parameters.at("\\LUT");
lut_default_state = RTLIL::State::Sx;
- module->add(cell);
continue;
}
}
std::set<std::string> delete_wires;
- std::set<std::string> delete_cells;
+ std::set<RTLIL::Cell*> delete_cells;
std::set<std::string> delete_procs;
std::set<std::string> delete_mems;
for (auto &it : module->cells) {
if (design->selected(module, it.second))
- delete_cells.insert(it.first);
+ delete_cells.insert(it.second);
if ((it.second->type == "$memrd" || it.second->type == "$memwr") &&
delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0)
- delete_cells.insert(it.first);
+ delete_cells.insert(it.second);
}
for (auto &it : module->processes)
}
for (auto &it : delete_cells) {
- delete module->cells.at(it);
- module->cells.erase(it);
+ module->remove(it);
}
for (auto &it : delete_procs) {
RTLIL::SigSpec new_sig = sig;
if (sig_a.size() != sig.size()) {
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$slice";
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$slice");
cell->parameters["\\OFFSET"] = offset;
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\Y_WIDTH"] = sig.size();
cell->connections["\\A"] = sig_a;
cell->connections["\\Y"] = module->addWire(NEW_ID, sig.size());
new_sig = cell->connections["\\Y"];
- module->add(cell);
}
sliced_signals_cache[sig] = new_sig;
RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
for (size_t i = 1; i < chunks.size(); i++) {
RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$concat";
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
cell->parameters["\\A_WIDTH"] = new_sig.size();
cell->parameters["\\B_WIDTH"] = sig2.size();
cell->connections["\\A"] = new_sig;
cell->connections["\\B"] = sig2;
cell->connections["\\Y"] = module->addWire(NEW_ID, new_sig.size() + sig2.size());
new_sig = cell->connections["\\Y"];
- module->add(cell);
}
spliced_signals_cache[sig] = new_sig;
merge_cell_into_fsm(c);
}
- for (auto c : merged_set) {
- module->cells.erase(c->name);
- delete c;
- }
+ for (auto c : merged_set)
+ module->remove(c);
if (merged_set.size() > 0 && !already_optimized)
FsmData::optimize_fsm(fsm_cell, module);
// create fsm cell
- RTLIL::Cell *fsm_cell = new RTLIL::Cell;
- fsm_cell->name = stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++);
- fsm_cell->type = "$fsm";
+ RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), RTLIL::autoidx++), "$fsm");
fsm_cell->connections["\\CLK"] = clk;
fsm_cell->connections["\\ARST"] = arst;
fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1);
fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name);
fsm_cell->attributes = wire->attributes;
fsm_data.copy_to_cell(fsm_cell);
- module->cells[fsm_cell->name] = fsm_cell;
// rename original state wire
if (eq_sig_a.size() > 0)
{
- RTLIL::Wire *eq_wire = new RTLIL::Wire;
- eq_wire->name = NEW_ID;
- module->add(eq_wire);
+ RTLIL::Wire *eq_wire = module->addWire(NEW_ID);
+ and_sig.append(RTLIL::SigSpec(eq_wire));
- RTLIL::Cell *eq_cell = new RTLIL::Cell;
- eq_cell->name = NEW_ID;
- eq_cell->type = "$eq";
+ RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
eq_cell->connections["\\A"] = eq_sig_a;
eq_cell->connections["\\B"] = eq_sig_b;
eq_cell->connections["\\Y"] = RTLIL::SigSpec(eq_wire);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size());
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.size());
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- module->add(eq_cell);
-
- and_sig.append(RTLIL::SigSpec(eq_wire));
}
if (or_sig.size() < num_states-int(fullstate_cache.size()))
}
else
{
- RTLIL::Wire *or_wire = new RTLIL::Wire;
- or_wire->name = NEW_ID;
- module->add(or_wire);
+ RTLIL::Wire *or_wire = module->addWire(NEW_ID);
+ and_sig.append(RTLIL::SigSpec(or_wire));
- RTLIL::Cell *or_cell = new RTLIL::Cell;
- or_cell->name = NEW_ID;
- or_cell->type = "$reduce_or";
+ RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
or_cell->connections["\\A"] = or_sig;
or_cell->connections["\\Y"] = RTLIL::SigSpec(or_wire);
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size());
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- module->add(or_cell);
-
- and_sig.append(RTLIL::SigSpec(or_wire));
}
}
{
case 2:
{
- RTLIL::Wire *and_wire = new RTLIL::Wire;
- and_wire->name = NEW_ID;
- module->add(and_wire);
+ RTLIL::Wire *and_wire = module->addWire(NEW_ID);
+ cases_vector.append(RTLIL::SigSpec(and_wire));
- RTLIL::Cell *and_cell = new RTLIL::Cell;
- and_cell->name = NEW_ID;
- and_cell->type = "$and";
+ RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and");
and_cell->connections["\\A"] = and_sig.extract(0, 1);
and_cell->connections["\\B"] = and_sig.extract(1, 1);
and_cell->connections["\\Y"] = RTLIL::SigSpec(and_wire);
and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1);
and_cell->parameters["\\B_WIDTH"] = RTLIL::Const(1);
and_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- module->add(and_cell);
-
- cases_vector.append(RTLIL::SigSpec(and_wire));
break;
}
case 1:
}
if (cases_vector.size() > 1) {
- RTLIL::Cell *or_cell = new RTLIL::Cell;
- or_cell->name = NEW_ID;
- or_cell->type = "$reduce_or";
+ RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
or_cell->connections["\\A"] = cases_vector;
or_cell->connections["\\Y"] = output;
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size());
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- module->add(or_cell);
} else if (cases_vector.size() == 1) {
module->connections.push_back(RTLIL::SigSig(output, cases_vector));
} else {
state_wire->width = fsm_data.state_bits;
module->add(state_wire);
- RTLIL::Wire *next_state_wire = new RTLIL::Wire;
- next_state_wire->name = NEW_ID;
- next_state_wire->width = fsm_data.state_bits;
- module->add(next_state_wire);
+ RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
- RTLIL::Cell *state_dff = new RTLIL::Cell;
- state_dff->name = NEW_ID;
+ RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
if (fsm_cell->connections["\\ARST"].is_fully_const()) {
state_dff->type = "$dff";
} else {
state_dff->connections["\\CLK"] = fsm_cell->connections["\\CLK"];
state_dff->connections["\\D"] = RTLIL::SigSpec(next_state_wire);
state_dff->connections["\\Q"] = RTLIL::SigSpec(state_wire);
- module->add(state_dff);
// decode state register
bool encoding_is_onehot = true;
- RTLIL::Wire *state_onehot = new RTLIL::Wire;
- state_onehot->name = NEW_ID;
- state_onehot->width = fsm_data.state_table.size();
- module->add(state_onehot);
+ RTLIL::Wire *state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size());
for (size_t i = 0; i < fsm_data.state_table.size(); i++)
{
{
encoding_is_onehot = false;
- RTLIL::Cell *eq_cell = new RTLIL::Cell;
- eq_cell->name = NEW_ID;
- eq_cell->type = "$eq";
+ RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
eq_cell->connections["\\A"] = sig_a;
eq_cell->connections["\\B"] = sig_b;
eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, i);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.size());
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- module->add(eq_cell);
}
}
}
}
- RTLIL::Cell *mux_cell = new RTLIL::Cell;
- mux_cell->name = NEW_ID;
- mux_cell->type = "$safe_pmux";
+ RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$safe_pmux");
mux_cell->connections["\\A"] = sig_a;
mux_cell->connections["\\B"] = sig_b;
mux_cell->connections["\\S"] = sig_s;
mux_cell->connections["\\Y"] = RTLIL::SigSpec(next_state_wire);
mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
- module->add(mux_cell);
}
// Generate ctrl_out signal
// Remove FSM cell
- module->cells.erase(fsm_cell->name);
- delete fsm_cell;
+ module->remove(fsm_cell);
}
struct FsmMapPass : public Pass {
}
for (RTLIL::Cell *cell : submod.cells) {
- RTLIL::Cell *new_cell = new RTLIL::Cell(*cell);
+ RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell->type);
+ new_cell->connections = cell->connections;
+ new_cell->parameters = cell->parameters;
+ new_cell->attributes = cell->attributes;
for (auto &conn : new_cell->connections)
for (auto &bit : conn.second)
if (bit.wire != NULL) {
bit.wire = wire_flags[bit.wire].new_wire;
}
log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());
- new_mod->cells[new_cell->name] = new_cell;
- module->cells.erase(cell->name);
- delete cell;
+ module->remove(cell);
}
submod.cells.clear();
- RTLIL::Cell *new_cell = new RTLIL::Cell;
- new_cell->name = submod.full_name;
- new_cell->type = submod.full_name;
+ RTLIL::Cell *new_cell = module->addCell(submod.full_name, submod.full_name);
for (auto &it : wire_flags)
{
RTLIL::Wire *old_wire = it.first;
if (new_wire->port_id > 0)
new_cell->connections[new_wire->name] = RTLIL::SigSpec(old_wire);
}
- module->cells[new_cell->name] = new_cell;
}
SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, std::string opt_name = std::string()) : design(design), module(module), opt_name(opt_name)
RTLIL::SigSpec sig_rd_addr;
RTLIL::SigSpec sig_rd_data;
- std::vector<std::string> del_cell_ids;
+ std::vector<RTLIL::Cell*> del_cells;
std::vector<RTLIL::Cell*> memcells;
for (auto &cell_it : module->cells) {
if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name)
{
wr_ports++;
- del_cell_ids.push_back(cell->name);
+ del_cells.push_back(cell);
RTLIL::SigSpec clk = cell->connections["\\CLK"];
RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
if (cell->type == "$memrd" && cell->parameters["\\MEMID"].decode_string() == memory->name)
{
rd_ports++;
- del_cell_ids.push_back(cell->name);
+ del_cells.push_back(cell);
RTLIL::SigSpec clk = cell->connections["\\CLK"];
RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
std::stringstream sstr;
sstr << "$mem$" << memory->name << "$" << (RTLIL::autoidx++);
- RTLIL::Cell *mem = new RTLIL::Cell;
- mem->name = sstr.str();
- mem->type = "$mem";
-
+ RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem");
mem->parameters["\\MEMID"] = RTLIL::Const(memory->name);
mem->parameters["\\WIDTH"] = RTLIL::Const(memory->width);
mem->parameters["\\OFFSET"] = RTLIL::Const(memory->start_offset);
mem->connections["\\RD_ADDR"] = sig_rd_addr;
mem->connections["\\RD_DATA"] = sig_rd_data;
- for (auto &id : del_cell_ids) {
- delete module->cells[id];
- module->cells.erase(id);
- }
- module->cells[mem->name] = mem;
+ for (auto c : del_cells)
+ module->remove(c);
}
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
// delete unused memory cell
if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) {
- module->cells.erase(cell->name);
- delete cell;
+ module->remove(cell);
return;
}
}
else
{
- RTLIL::Cell *c = new RTLIL::Cell;
- c->name = genid(cell->name, "", i);
- c->type = "$dff";
+ RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff");
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
if (clocks_pol.bits.size() > 0) {
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1);
c->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::S0);
}
- module->cells[c->name] = c;
RTLIL::Wire *w_in = new RTLIL::Wire;
w_in->name = genid(cell->name, "", i, "$d");
{
if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1)
{
- RTLIL::Cell *c = new RTLIL::Cell;
- c->name = genid(cell->name, "$rdreg", i);
- c->type = "$dff";
+ RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1);
c->connections["\\D"] = rd_addr;
- module->cells[c->name] = c;
count_dff++;
RTLIL::Wire *w = new RTLIL::Wire;
}
else
{
- RTLIL::Cell *c = new RTLIL::Cell;
- c->name = genid(cell->name, "$rdreg", i);
- c->type = "$dff";
+ RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1);
c->connections["\\Q"] = rd_signals.back();
- module->cells[c->name] = c;
count_dff++;
RTLIL::Wire *w = new RTLIL::Wire;
for (size_t k = 0; k < rd_signals.size(); k++)
{
- RTLIL::Cell *c = new RTLIL::Cell;
- c->name = genid(cell->name, "$rdmux", i, "", j, "", k);
- c->type = "$mux";
+ RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux");
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
c->connections["\\Y"] = rd_signals[k];
c->connections["\\S"] = rd_addr.extract(mem_abits-j-1, 1);
- module->cells[c->name] = c;
count_mux++;
RTLIL::Wire *w = new RTLIL::Wire;
RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(j*mem_width, mem_width);
RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j*mem_width, mem_width);
- RTLIL::Cell *c = new RTLIL::Cell;
- c->name = genid(cell->name, "$wreq", i, "", j);
- c->type = "$eq";
+ RTLIL::Cell *c = module->addCell(genid(cell->name, "$wreq", i, "", j), "$eq");
c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"];
c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
c->connections["\\A"] = RTLIL::SigSpec(i, mem_abits);
c->connections["\\B"] = wr_addr;
- module->cells[c->name] = c;
count_wrmux++;
RTLIL::Wire *w_seladdr = new RTLIL::Wire;
if (wr_bit != RTLIL::SigSpec(1, 1))
{
- c = new RTLIL::Cell;
- c->name = genid(cell->name, "$wren", i, "", j, "", wr_offset);
- c->type = "$and";
+ c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and");
c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
c->connections["\\A"] = w;
c->connections["\\B"] = wr_bit;
- module->cells[c->name] = c;
w = new RTLIL::Wire;
w->name = genid(cell->name, "$wren", i, "", j, "", wr_offset, "$y");
c->connections["\\Y"] = RTLIL::SigSpec(w);
}
- c = new RTLIL::Cell;
- c->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset);
- c->type = "$mux";
+ c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux");
c->parameters["\\WIDTH"] = wr_width;
c->connections["\\A"] = sig.extract(wr_offset, wr_width);
c->connections["\\B"] = wr_data.extract(wr_offset, wr_width);
c->connections["\\S"] = RTLIL::SigSpec(w);
- module->cells[c->name] = c;
w = new RTLIL::Wire;
w->name = genid(cell->name, "$wrmux", i, "", j, "", wr_offset, "$y");
log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux);
- module->cells.erase(cell->name);
- delete cell;
- return;
+ module->remove(cell);
}
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
cell->connections.at("\\EN") = merged_en;
cell->connections.at("\\DATA") = merged_data;
- module->cells.erase(wr_ports[last_i]->name);
- delete wr_ports[last_i];
+ module->remove(wr_ports[last_i]);
wr_ports[last_i] = NULL;
log(" Active bits: ");
module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
wr_ports[i]->connections.at("\\EN") = en;
- module->cells.erase(wr_ports[i-1]->name);
- delete wr_ports[i-1];
+ module->remove(wr_ports[i-1]);
wr_ports[i-1] = NULL;
}
for (int i = 0; i < num_rd_ports; i++)
{
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$memrd";
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd");
cell->parameters["\\MEMID"] = mem_name;
cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
cell->connections["\\CLK"] = memory->connections.at("\\RD_CLK").extract(i, 1);
cell->connections["\\ADDR"] = memory->connections.at("\\RD_ADDR").extract(i*abits, abits);
cell->connections["\\DATA"] = memory->connections.at("\\RD_DATA").extract(i*mem->width, mem->width);
- module->add(cell);
}
for (int i = 0; i < num_wr_ports; i++)
{
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$memwr";
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr");
cell->parameters["\\MEMID"] = mem_name;
cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i*mem->width, mem->width);
cell->connections["\\ADDR"] = memory->connections.at("\\WR_ADDR").extract(i*abits, abits);
cell->connections["\\DATA"] = memory->connections.at("\\WR_DATA").extract(i*mem->width, mem->width);
- module->add(cell);
}
- module->cells.erase(memory->name);
- delete memory;
+ module->remove(memory);
}
static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
if (verbose)
log(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str());
OPT_DID_SOMETHING = true;
- module->cells.erase(cell->name);
+ module->remove(cell);
count_rm_cells++;
- delete cell;
}
}
module->name.c_str(), log_signal(Y), log_signal(out_val));
// ILANG_BACKEND::dump_cell(stderr, "--> ", cell);
module->connections.push_back(RTLIL::SigSig(Y, out_val));
- module->cells.erase(cell->name);
- delete cell;
+ module->remove(cell);
OPT_DID_SOMETHING = true;
did_something = true;
}
continue;
if (live_ports.size() == 0) {
- module->cells.erase(mi.cell->name);
- delete mi.cell;
+ module->remove(mi.cell);
continue;
}
{
RTLIL::SigSpec sig_in = sig_ports.extract(live_ports[0]*sig_a.size(), sig_a.size());
module->connections.push_back(RTLIL::SigSig(sig_y, sig_in));
- module->cells.erase(mi.cell->name);
- delete mi.cell;
+ module->remove(mi.cell);
}
else
{
if (this_s.size() > 1)
{
- RTLIL::Wire *reduce_or_wire = new RTLIL::Wire;
- reduce_or_wire->name = NEW_ID;
- module->wires[reduce_or_wire->name] = reduce_or_wire;
-
- RTLIL::Cell *reduce_or_cell = new RTLIL::Cell;
- reduce_or_cell->name = NEW_ID;
- reduce_or_cell->type = "$reduce_or";
+ RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, "$reduce_or");
reduce_or_cell->connections["\\A"] = this_s;
reduce_or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
reduce_or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(this_s.size());
reduce_or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
- module->cells[reduce_or_cell->name] = reduce_or_cell;
+ RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
this_s = RTLIL::SigSpec(reduce_or_wire);
reduce_or_cell->connections["\\Y"] = this_s;
}
{
module->connections.push_back(RTLIL::SigSig(cell->connections["\\Y"], cell->connections["\\A"]));
assign_map.add(cell->connections["\\Y"], cell->connections["\\A"]);
- module->cells.erase(cell->name);
- delete cell;
+ module->remove(cell);
}
else
{
delete_dff:
log("Removing %s (%s) from module %s.\n", dff->name.c_str(), dff->type.c_str(), mod->name.c_str());
OPT_DID_SOMETHING = true;
- mod->cells.erase(dff->name);
- delete dff;
+ mod->remove(dff);
return true;
}
}
}
log(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
- module->cells.erase(cell->name);
+ module->remove(cell);
OPT_DID_SOMETHING = true;
total_count++;
- delete cell;
} else {
sharemap[cell] = cell;
}
log_abort();
if (sync_low_signals.size() > 1) {
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$reduce_or";
+ RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or");
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->connections["\\A"] = sync_low_signals;
cell->connections["\\Y"] = sync_low_signals = mod->addWire(NEW_ID);
- mod->add(cell);
}
if (sync_low_signals.size() > 0) {
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$not";
+ RTLIL::Cell *cell = mod->addCell(NEW_ID, "$not");
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->connections["\\A"] = sync_low_signals;
cell->connections["\\Y"] = mod->addWire(NEW_ID);
sync_high_signals.append(cell->connections["\\Y"]);
- mod->add(cell);
}
if (sync_high_signals.size() > 1) {
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$reduce_or";
+ RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or");
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
cell->connections["\\A"] = sync_high_signals;
cell->connections["\\Y"] = sync_high_signals = mod->addWire(NEW_ID);
- mod->add(cell);
}
- RTLIL::Cell *inv_cell = new RTLIL::Cell;
- inv_cell->name = NEW_ID;
- inv_cell->type = "$not";
+ RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not");
inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size());
inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size());
inv_cell->connections["\\A"] = sync_value;
inv_cell->connections["\\Y"] = sync_value_inv = mod->addWire(NEW_ID, sig_d.size());
- mod->add(inv_cell);
- RTLIL::Cell *mux_set_cell = new RTLIL::Cell;
- mux_set_cell->name = NEW_ID;
- mux_set_cell->type = "$mux";
+ RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux");
mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
mux_set_cell->connections["\\A"] = sig_sr_set;
mux_set_cell->connections["\\B"] = sync_value;
mux_set_cell->connections["\\S"] = sync_high_signals;
mux_set_cell->connections["\\Y"] = sig_sr_set = mod->addWire(NEW_ID, sig_d.size());
- mod->add(mux_set_cell);
- RTLIL::Cell *mux_clr_cell = new RTLIL::Cell;
- mux_clr_cell->name = NEW_ID;
- mux_clr_cell->type = "$mux";
+ RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux");
mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
mux_clr_cell->connections["\\A"] = sig_sr_clr;
mux_clr_cell->connections["\\B"] = sync_value_inv;
mux_clr_cell->connections["\\S"] = sync_high_signals;
mux_clr_cell->connections["\\Y"] = sig_sr_clr = mod->addWire(NEW_ID, sig_d.size());
- mod->add(mux_clr_cell);
}
std::stringstream sstr;
sstr << "$procdff$" << (RTLIL::autoidx++);
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = sstr.str();
- cell->type = "$dffsr";
+ RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
cell->attributes = proc->attributes;
cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
cell->connections["\\CLK"] = clk;
cell->connections["\\SET"] = sig_sr_set;
cell->connections["\\CLR"] = sig_sr_clr;
- mod->add(cell);
log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size());
RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size());
- RTLIL::Cell *inv_set = new RTLIL::Cell;
- inv_set->name = NEW_ID;
- inv_set->type = "$not";
+ RTLIL::Cell *inv_set = mod->addCell(NEW_ID, "$not");
inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0);
inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size());
inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size());
inv_set->connections["\\A"] = sig_set;
inv_set->connections["\\Y"] = sig_set_inv;
- mod->add(inv_set);
- RTLIL::Cell *mux_sr_set = new RTLIL::Cell;
- mux_sr_set->name = NEW_ID;
- mux_sr_set->type = "$mux";
+ RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux");
mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
mux_sr_set->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
mux_sr_set->connections[set_polarity ? "\\B" : "\\A"] = sig_set;
mux_sr_set->connections["\\Y"] = sig_sr_set;
mux_sr_set->connections["\\S"] = set;
- mod->add(mux_sr_set);
- RTLIL::Cell *mux_sr_clr = new RTLIL::Cell;
- mux_sr_clr->name = NEW_ID;
- mux_sr_clr->type = "$mux";
+ RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux");
mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
mux_sr_clr->connections[set_polarity ? "\\A" : "\\B"] = RTLIL::Const(0, sig_in.size());
mux_sr_clr->connections[set_polarity ? "\\B" : "\\A"] = sig_set_inv;
mux_sr_clr->connections["\\Y"] = sig_sr_clr;
mux_sr_clr->connections["\\S"] = set;
- mod->add(mux_sr_clr);
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = sstr.str();
- cell->type = "$dffsr";
+ RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
cell->attributes = proc->attributes;
cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
cell->connections["\\CLK"] = clk;
cell->connections["\\SET"] = sig_sr_set;
cell->connections["\\CLR"] = sig_sr_clr;
- mod->add(cell);
log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
std::stringstream sstr;
sstr << "$procdff$" << (RTLIL::autoidx++);
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = sstr.str();
- cell->type = arst ? "$adff" : "$dff";
+ RTLIL::Cell *cell = mod->addCell(sstr.str(), arst ? "$adff" : "$dff");
cell->attributes = proc->attributes;
- mod->cells[cell->name] = cell;
cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
if (arst) {
}
assert(inputs.size() == compare.size());
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = "$ne";
+ RTLIL::Cell *cell = mod->addCell(NEW_ID, "$ne");
cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1);
cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size());
cell->connections["\\A"] = inputs;
cell->connections["\\B"] = compare;
cell->connections["\\Y"] = sync_level->signal;
- mod->add(cell);
many_async_rules.clear();
}
else
{
// create compare cell
- RTLIL::Cell *eq_cell = new RTLIL::Cell;
- std::stringstream sstr2;
- sstr2 << sstr.str() << "_CMP" << cmp_wire->width;
- eq_cell->name = sstr2.str();
- eq_cell->type = "$eq";
+ RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), "$eq");
eq_cell->attributes = sw->attributes;
- mod->cells[eq_cell->name] = eq_cell;
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0);
mod->wires[ctrl_wire->name] = ctrl_wire;
// reduce cmp vector to one logic signal
- RTLIL::Cell *any_cell = new RTLIL::Cell;
- any_cell->name = sstr.str() + "_ANY";
- any_cell->type = "$reduce_or";
+ RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or");
any_cell->attributes = sw->attributes;
- mod->cells[any_cell->name] = any_cell;
any_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width);
mod->wires[result_wire->name] = result_wire;
// create the multiplexer itself
- RTLIL::Cell *mux_cell = new RTLIL::Cell;
- mux_cell->name = sstr.str();
- mux_cell->type = "$mux";
+ RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux");
mux_cell->attributes = sw->attributes;
- mod->cells[mux_cell->name] = mux_cell;
mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size());
mux_cell->connections["\\A"] = else_signal;
if (info.clk_polarity) {
module->connections.push_back(RTLIL::SigSig(wire_c, info.sig_clk));
} else {
- RTLIL::Cell *c = new RTLIL::Cell;
- c->name = NEW_ID;
- c->type = "$not";
+ RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
c->parameters["\\A_SIGNED"] = 0;
c->parameters["\\A_WIDTH"] = 1;
c->parameters["\\Y_WIDTH"] = 1;
c->connections["\\A"] = info.sig_clk;
c->connections["\\Y"] = wire_c;
- module->add(c);
}
if (info.sig_arst != RTLIL::State::Sm)
if (info.arst_polarity) {
module->connections.push_back(RTLIL::SigSig(wire_r, info.sig_arst));
} else {
- RTLIL::Cell *c = new RTLIL::Cell;
- c->name = NEW_ID;
- c->type = "$not";
+ RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
c->parameters["\\A_SIGNED"] = 0;
c->parameters["\\A_WIDTH"] = 1;
c->parameters["\\Y_WIDTH"] = 1;
c->connections["\\A"] = info.sig_arst;
c->connections["\\Y"] = wire_r;
- module->add(c);
}
RTLIL::Wire *wire_v = new RTLIL::Wire;
if (flag_evert)
{
- std::vector<std::string> delete_cells;
+ std::vector<RTLIL::Cell*> delete_cells;
for (auto &it : module->cells)
{
}
}
- delete_cells.push_back(cell->name);
+ delete_cells.push_back(cell);
}
- for (auto &it : delete_cells) {
- log("Removing cell: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it), RTLIL::id2cstr(module->cells.at(it)->type));
- delete module->cells.at(it);
- module->cells.erase(it);
+ for (auto cell : delete_cells) {
+ log("Removing cell: %s/%s (%s)\n", log_id(module), log_id(cell), log_id(cell->type));
+ module->remove(cell);
}
}
{
inv_sig = module->addWire(NEW_ID);
- RTLIL::Cell *inv_cell = new RTLIL::Cell;
- inv_cell->name = NEW_ID;
- inv_cell->type = "$_INV_";
+ RTLIL::Cell *inv_cell = module->addCell(NEW_ID, "$_INV_");
inv_cell->connections["\\A"] = grp[0].bit;
inv_cell->connections["\\Y"] = inv_sig;
- module->add(inv_cell);
}
module->connections.push_back(RTLIL::SigSig(grp[i].bit, inv_sig));
miter_module->name = miter_name;
design->modules[miter_name] = miter_module;
- RTLIL::Cell *gold_cell = new RTLIL::Cell;
- gold_cell->name = "\\gold";
- gold_cell->type = gold_name;
- miter_module->add(gold_cell);
-
- RTLIL::Cell *gate_cell = new RTLIL::Cell;
- gate_cell->name = "\\gate";
- gate_cell->type = gate_name;
- miter_module->add(gate_cell);
+ RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name);
+ RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name);
RTLIL::SigSpec all_conditions;
{
RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w2_gold->width);
for (int i = 0; i < w2_gold->width; i++) {
- RTLIL::Cell *eqx_cell = new RTLIL::Cell;
- eqx_cell->name = NEW_ID;
- eqx_cell->type = "$eqx";
+ RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, "$eqx");
eqx_cell->parameters["\\A_WIDTH"] = 1;
eqx_cell->parameters["\\B_WIDTH"] = 1;
eqx_cell->parameters["\\Y_WIDTH"] = 1;
eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, i);
eqx_cell->connections["\\B"] = RTLIL::State::Sx;
eqx_cell->connections["\\Y"] = gold_x.extract(i, 1);
- miter_module->add(eqx_cell);
}
RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width);
RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w2_gate->width);
- RTLIL::Cell *or_gold_cell = new RTLIL::Cell;
- or_gold_cell->name = NEW_ID;
- or_gold_cell->type = "$or";
+ RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, "$or");
or_gold_cell->parameters["\\A_WIDTH"] = w2_gold->width;
or_gold_cell->parameters["\\B_WIDTH"] = w2_gold->width;
or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width;
or_gold_cell->connections["\\A"] = w2_gold;
or_gold_cell->connections["\\B"] = gold_x;
or_gold_cell->connections["\\Y"] = gold_masked;
- miter_module->add(or_gold_cell);
- RTLIL::Cell *or_gate_cell = new RTLIL::Cell;
- or_gate_cell->name = NEW_ID;
- or_gate_cell->type = "$or";
+ RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or");
or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width;
or_gate_cell->parameters["\\B_WIDTH"] = w2_gate->width;
or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width;
or_gate_cell->connections["\\A"] = w2_gate;
or_gate_cell->connections["\\B"] = gold_x;
or_gate_cell->connections["\\Y"] = gate_masked;
- miter_module->add(or_gate_cell);
- RTLIL::Cell *eq_cell = new RTLIL::Cell;
- eq_cell->name = NEW_ID;
- eq_cell->type = "$eqx";
+ RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
eq_cell->parameters["\\Y_WIDTH"] = 1;
eq_cell->connections["\\B"] = gate_masked;
eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID);
this_condition = eq_cell->connections["\\Y"];
- miter_module->add(eq_cell);
}
else
{
- RTLIL::Cell *eq_cell = new RTLIL::Cell;
- eq_cell->name = NEW_ID;
- eq_cell->type = "$eqx";
+ RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
eq_cell->parameters["\\Y_WIDTH"] = 1;
eq_cell->connections["\\B"] = w2_gate;
eq_cell->connections["\\Y"] = miter_module->addWire(NEW_ID);
this_condition = eq_cell->connections["\\Y"];
- miter_module->add(eq_cell);
}
if (flag_make_outcmp)
}
if (all_conditions.size() != 1) {
- RTLIL::Cell *reduce_cell = new RTLIL::Cell;
- reduce_cell->name = NEW_ID;
- reduce_cell->type = "$reduce_and";
+ RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, "$reduce_and");
reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size();
reduce_cell->parameters["\\Y_WIDTH"] = 1;
reduce_cell->parameters["\\A_SIGNED"] = 0;
reduce_cell->connections["\\A"] = all_conditions;
reduce_cell->connections["\\Y"] = miter_module->addWire(NEW_ID);
all_conditions = reduce_cell->connections["\\Y"];
- miter_module->add(reduce_cell);
}
if (flag_make_assert) {
- RTLIL::Cell *assert_cell = new RTLIL::Cell;
- assert_cell->name = NEW_ID;
- assert_cell->type = "$assert";
+ RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert");
assert_cell->connections["\\A"] = all_conditions;
assert_cell->connections["\\EN"] = RTLIL::SigSpec(1, 1);
- miter_module->add(assert_cell);
}
RTLIL::Wire *w_trigger = new RTLIL::Wire;
w_trigger->port_output = true;
miter_module->add(w_trigger);
- RTLIL::Cell *not_cell = new RTLIL::Cell;
- not_cell->name = NEW_ID;
- not_cell->type = "$not";
+ RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, "$not");
not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
not_cell->parameters["\\A_SIGNED"] = 0;
not_cell->connections["\\A"] = all_conditions;
not_cell->connections["\\Y"] = w_trigger;
- miter_module->add(not_cell);
miter_module->fixup_ports();
RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
- RTLIL::Cell *supercell = new RTLIL::Cell;
- supercell->name = NEW_ID;
- supercell->type = c1->type;
+ RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
supercell->parameters["\\A_SIGNED"] = a_signed;
supercell->parameters["\\A_WIDTH"] = a_width;
supercell->parameters["\\Y_WIDTH"] = y_width;
supercell->connections["\\A"] = a;
supercell->connections["\\Y"] = y;
- module->add(supercell);
RTLIL::SigSpec new_y1(y, 0, y1.size());
RTLIL::SigSpec new_y2(y, 0, y2.size());
log("Removing %d cells in module %s:\n", SIZE(cells_to_remove), log_id(module));
for (auto c : cells_to_remove) {
log(" Removing cell %s (%s).\n", log_id(c), log_id(c->type));
- module->cells.erase(c->name);
- delete c;
+ module->remove(c);
}
}
}
std::map<std::string, int> stats;
- for (auto cell : cell_list) {
- cell_mapping &cm = cell_mappings[cell->type];
- RTLIL::Cell *new_cell = new RTLIL::Cell;
- new_cell->name = cell->name;
- new_cell->type = "\\" + cm.cell_name;
+ for (auto cell : cell_list)
+ {
+ auto cell_type = cell->type;
+ auto cell_name = cell->name;
+ auto cell_connections = cell->connections;
+ module->remove(cell);
+
+ cell_mapping &cm = cell_mappings[cell_type];
+ RTLIL::Cell *new_cell = module->addCell(cell_name, "\\" + cm.cell_name);
+
for (auto &port : cm.ports) {
RTLIL::SigSpec sig;
if ('A' <= port.second && port.second <= 'Z') {
- sig = cell->connections[std::string("\\") + port.second];
+ sig = cell_connections[std::string("\\") + port.second];
} else
if ('a' <= port.second && port.second <= 'z') {
- sig = cell->connections[std::string("\\") + char(port.second - ('a' - 'A'))];
- RTLIL::Cell *inv_cell = new RTLIL::Cell;
- RTLIL::Wire *inv_wire = new RTLIL::Wire;
- inv_cell->name = stringf("$dfflibmap$inv$%d", RTLIL::autoidx);
- inv_wire->name = stringf("$dfflibmap$sig$%d", RTLIL::autoidx++);
- inv_cell->type = "$_INV_";
- inv_cell->connections[port.second == 'q' ? "\\Y" : "\\A"] = sig;
- sig = RTLIL::SigSpec(inv_wire);
- inv_cell->connections[port.second == 'q' ? "\\A" : "\\Y"] = sig;
- module->cells[inv_cell->name] = inv_cell;
- module->wires[inv_wire->name] = inv_wire;
+ sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
+ sig = module->InvGate(NEW_ID, sig);
} else
if (port.second == '0' || port.second == '1') {
sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);
log_abort();
new_cell->connections["\\" + port.first] = sig;
}
- stats[stringf(" mapped %%d %s cells to %s cells.\n", cell->type.c_str(), new_cell->type.c_str())]++;
- module->cells[cell->name] = new_cell;
- delete cell;
+
+ stats[stringf(" mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++;
}
for (auto &stat: stats)
SigSet<std::pair<std::string, int>> sig2port;
// create new cell
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++);
- cell->type = needle->name;
- haystack->add(cell);
+ RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), RTLIL::autoidx++), needle->name);
// create cell ports
for (auto &it : needle->wires) {
}
}
- haystack->cells.erase(haystack_cell->name);
- delete haystack_cell;
+ haystack->remove(haystack_cell);
}
return cell;
}
for (auto cell : cells) {
- RTLIL::Cell *newCell = new RTLIL::Cell;
- newCell->name = cell->name;
- newCell->type = cell->type;
+ RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
newCell->parameters = cell->parameters;
for (auto &conn : cell->connections) {
std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
chunk.wire = newMod->wires.at(chunk.wire->name);
newCell->connections[conn.first] = chunks;
}
- newMod->add(newCell);
}
}
if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi == RTLIL::State::Sm) {
last_hi = module->addWire(NEW_ID);
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = RTLIL::escape_id(hicell_celltype);
+ RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
cell->connections[RTLIL::escape_id(hicell_portname)] = last_hi;
- module->add(cell);
}
bit = last_hi;
}
if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
if (!singleton_mode || last_lo == RTLIL::State::Sm) {
last_lo = module->addWire(NEW_ID);
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = RTLIL::escape_id(locell_celltype);
+ RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
cell->connections[RTLIL::escape_id(locell_portname)] = last_lo;
- module->add(cell);
}
bit = last_lo;
}
{
for (int i = 0; i < wire->width; i++)
{
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = RTLIL::escape_id(celltype);
+ RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
if (!portname2.empty())
cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
cell->attributes["\\keep"] = RTLIL::Const(1);
- module->add(cell);
}
}
else
{
- RTLIL::Cell *cell = new RTLIL::Cell;
- cell->name = NEW_ID;
- cell->type = RTLIL::escape_id(celltype);
+ RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire);
if (!portname2.empty())
cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire);
if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
cell->attributes["\\keep"] = RTLIL::Const(1);
- module->add(cell);
}
wire->port_id = 0;
sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
for (int i = 0; i < SIZE(sig_y); i++) {
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = "$_INV_";
+ RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
gate->connections["\\A"] = sig_a[i];
gate->connections["\\Y"] = sig_y[i];
- module->add(gate);
}
}
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, SIZE(sig_y));
for (int i = 0; i < SIZE(sig_y); i++) {
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = "$_INV_";
+ RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
gate->connections["\\A"] = sig_t[i];
gate->connections["\\Y"] = sig_y[i];
- module->add(gate);
}
sig_y = sig_t;
log_assert(!gate_type.empty());
for (int i = 0; i < SIZE(sig_y); i++) {
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = gate_type;
+ RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->connections["\\A"] = sig_a[i];
gate->connections["\\B"] = sig_b[i];
gate->connections["\\Y"] = sig_y[i];
- module->add(gate);
}
}
continue;
}
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = gate_type;
+ RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->connections["\\A"] = sig_a[i];
gate->connections["\\B"] = sig_a[i+1];
gate->connections["\\Y"] = sig_t[i/2];
last_output = &gate->connections["\\Y"];
- module->add(gate);
}
sig_a = sig_t;
if (cell->type == "$reduce_xnor") {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = "$_INV_";
+ RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
gate->connections["\\A"] = sig_a;
gate->connections["\\Y"] = sig_t;
last_output = &gate->connections["\\Y"];
- module->add(gate);
sig_a = sig_t;
}
continue;
}
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = "$_OR_";
+ RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_");
gate->connections["\\A"] = sig[i];
gate->connections["\\B"] = sig[i+1];
gate->connections["\\Y"] = sig_t[i/2];
- module->add(gate);
}
sig = sig_t;
sig_y = sig_y.extract(0, 1);
}
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = "$_INV_";
+ RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
gate->connections["\\A"] = sig_a;
gate->connections["\\Y"] = sig_y;
- module->add(gate);
}
static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == "$logic_or") gate_type = "$_OR_";
log_assert(!gate_type.empty());
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = gate_type;
+ RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->connections["\\A"] = sig_a;
gate->connections["\\B"] = sig_b;
gate->connections["\\Y"] = sig_y;
- module->add(gate);
}
static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
for (int i = 0; i < SIZE(sig_y); i++) {
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = "$_MUX_";
+ RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
gate->connections["\\A"] = sig_a[i];
gate->connections["\\B"] = sig_b[i];
gate->connections["\\S"] = cell->connections.at("\\S");
gate->connections["\\Y"] = sig_y[i];
- module->add(gate);
}
}
std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
for (int i = 0; i < width; i++) {
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = gate_type;
+ RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->connections["\\S"] = sig_s[i];
gate->connections["\\R"] = sig_r[i];
gate->connections["\\Q"] = sig_q[i];
- module->add(gate);
}
}
std::string gate_type = stringf("$_DFF_%c_", clk_pol);
for (int i = 0; i < width; i++) {
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = gate_type;
+ RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->connections["\\C"] = sig_clk;
gate->connections["\\D"] = sig_d[i];
gate->connections["\\Q"] = sig_q[i];
- module->add(gate);
}
}
std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
for (int i = 0; i < width; i++) {
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = gate_type;
+ RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->connections["\\C"] = sig_clk;
gate->connections["\\S"] = sig_s[i];
gate->connections["\\R"] = sig_r[i];
gate->connections["\\D"] = sig_d[i];
gate->connections["\\Q"] = sig_q[i];
- module->add(gate);
}
}
std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
for (int i = 0; i < width; i++) {
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0;
+ RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
gate->connections["\\C"] = sig_clk;
gate->connections["\\R"] = sig_rst;
gate->connections["\\D"] = sig_d[i];
gate->connections["\\Q"] = sig_q[i];
- module->add(gate);
}
}
std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
for (int i = 0; i < width; i++) {
- RTLIL::Cell *gate = new RTLIL::Cell;
- gate->name = NEW_ID;
- gate->type = gate_type;
+ RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->connections["\\E"] = sig_en;
gate->connections["\\D"] = sig_d[i];
gate->connections["\\Q"] = sig_q[i];
- module->add(gate);
}
}
mappers.at(cell_it.second->type)(mod_it.second, cell_it.second);
delete_cells.push_back(cell_it.second);
}
- for (auto &it : delete_cells) {
- mod_it.second->cells.erase(it->name);
- delete it;
- }
+ for (auto c : delete_cells)
+ mod_it.second->remove(c);
}
}
} SimplemapPass;
log_error("Technology map yielded processes -> this is not supported.\n");
}
- // erase from namespace first for _TECHMAP_REPLACE_ to work
- module->cells.erase(cell->name);
std::string orig_cell_name;
-
if (!flatten_mode)
for (auto &it : tpl->cells)
if (it.first == "\\_TECHMAP_REPLACE_") {
orig_cell_name = cell->name;
- cell->name = stringf("$techmap%d", RTLIL::autoidx++) + cell->name;
+ module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name);
break;
}
}
}
- for (auto &it : tpl->cells) {
- RTLIL::Cell *c = new RTLIL::Cell(*it.second);
- if (!flatten_mode && c->type.substr(0, 2) == "\\$")
- c->type = c->type.substr(1);
- if (!flatten_mode && c->name == "\\_TECHMAP_REPLACE_")
- c->name = orig_cell_name;
+ for (auto &it : tpl->cells)
+ {
+ RTLIL::IdString c_name = it.second->name;
+ RTLIL::IdString c_type = it.second->type;
+
+ if (!flatten_mode && c_type.substr(0, 2) == "\\$")
+ c_type = c_type.substr(1);
+
+ if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_")
+ c_name = orig_cell_name;
else
- apply_prefix(cell->name, c->name);
+ apply_prefix(cell->name, c_name);
+
+ RTLIL::Cell *c = module->addCell(c_name, c_type);
+ c->connections = it.second->connections;
+ c->parameters = it.second->parameters;
+ c->attributes = it.second->attributes;
+ design->select(module, c);
+
for (auto &it2 : c->connections) {
apply_prefix(cell->name, it2.second, module);
port_signal_map.apply(it2.second);
}
- module->add(c);
- design->select(module, c);
}
for (auto &it : tpl->connections) {
module->connections.push_back(c);
}
- delete cell;
+ module->remove(cell);
}
bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
if (simplemap_mappers.count(cell->type) == 0)
log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
simplemap_mappers.at(cell->type)(module, cell);
- module->cells.erase(cell->name);
- delete cell;
+ module->remove(cell);
cell = NULL;
did_something = true;
break;
projects / yosys.git / commitdiff