targets: remove sdcard clock domain (now generated in the PHY).

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index ea2b62c1fde93fd4892fb5c10c0f91e46131d49d..332031548c5bc2e8501a6529a7d79721757d3a32 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -30,7 +30,6 @@ class _CRG(Module):
         self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200    = ClockDomain()
         self.clock_domains.cd_eth       = ClockDomain()
-        self.clock_domains.cd_sd        = ClockDomain()
 
         # # #
 
@@ -42,7 +41,6 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_clk200,    200e6)
         pll.create_clkout(self.cd_eth,       50e6)
-        pll.create_clkout(self.cd_sd,        10e6)
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 70a58660cde2760d3a81f8cca4575d2495ddb109..aa92109241a87f5e2933cb3730f9df9da3eea7db 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -30,7 +30,6 @@ class _CRG(Module):
         self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200    = ClockDomain()
         self.clock_domains.cd_clk100    = ClockDomain()
-        self.clock_domains.cd_sd        = ClockDomain()
 
         # # #
 
@@ -42,7 +41,6 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_clk200,    200e6)
         pll.create_clkout(self.cd_clk100,    100e6)
-        pll.create_clkout(self.cd_sd,        10e6)
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 915eab8e192885b1c6f11badce184125a4a04ee3..98448974bf2d1765d14a97ba8212fa7626e238a4 100755 (executable)
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -32,7 +32,6 @@ class _CRG(Module):
     def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
-        self.clock_domains.cd_sd     = ClockDomain()
 
         # # #
 
@@ -46,9 +45,7 @@ class _CRG(Module):
         pll.register_clkin(clk25, 25e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
-        pll.create_clkout(self.cd_sd,     10e6)
         self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
-        self.specials += AsyncResetSynchronizer(self.cd_sd,  ~pll.locked | rst)
 
         # USB PLL
         if with_usb_pll: