fix compilation and use new cpu_csr_regions

diff --git a/Makefile b/Makefile
index 190bf115dd03ff709a50b6b7ce164a3ce703082a..da07f84e6e1a8596be192a536c09a8112e2970b6 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 MSCDIR = ../misoc
-CURDIR = ../sata_controller
+CURDIR = ../sata-controller
 PYTHON = python3
 TOOLCHAIN = vivado
 PLATFORM = kc705

diff --git a/lib/sata/phy/k7sataphy/datapath.py b/lib/sata/phy/k7sataphy/datapath.py
index 8facc6e02bd6c29b104cd9810765a837935c10ec..d28761f6c395684d1365d9fa1e6ae4ace81328cb 100644 (file)
--- a/lib/sata/phy/k7sataphy/datapath.py
+++ b/lib/sata/phy/k7sataphy/datapath.py
@@ -140,7 +140,7 @@ class K7SATAPHYDatapath(Module):
                receive_align = Signal()
                self.comb += receive_align.eq(rx.source.stb &
                                                (rx.source.charisk == 0b0001) &
-                                               (rx.source.data == primitives["ALIGN"])
+                                               (rx.source.data == primitives["ALIGN"]))
 
        # user / ctrl mux
                self.comb += [

diff --git a/targets/test.py b/targets/test.py
index e5e92e4cbef99ce03b11246e93a93c4ea67673ca..884c35d98b9adb6becbab1088dd3cb0fb0b63d9a 100644 (file)
--- a/targets/test.py
+++ b/targets/test.py
@@ -65,6 +65,8 @@ class UART2WB(Module):
                self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
                self._wb_masters = [self.uart2wb.wishbone]
                self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
+               self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
+
 
                # CSR
                self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
@@ -79,6 +81,12 @@ class UART2WB(Module):
                        raise FinalizeError
                self._wb_slaves.append((address_decoder, interface))
 
+       def add_cpu_memory_region(self, name, origin, length):
+               self.cpu_memory_regions.append((name, origin, length))
+
+       def add_cpu_csr_region(self, name, origin, busword, obj):
+               self.cpu_csr_regions.append((name, origin, busword, obj))
+
        def do_finalize(self):
                # Wishbone
                self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
@@ -89,6 +97,10 @@ class UART2WB(Module):
                        lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
                        data_width=self.csr_data_width)
                self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
+               for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
+                       self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
+               for name, memory, mapaddr, mmap in self.csrbankarray.srams:
+                       self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
 
 class SimDesign(UART2WB):
        default_platform = "kc705"
@@ -148,7 +160,7 @@ class TestDesign(UART2WB, AutoCSR):
                UART2WB.__init__(self, platform, clk_freq)
                self.submodules.crg = _CRG(platform)
 
-               self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True, default_speed="SATA2")
+               self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True, default_speed="SATA1")
                self.comb += [
                        self.sataphy_host.sink.stb.eq(1),
                        self.sataphy_host.sink.data.eq(primitives["SYNC"]),