Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 45d7a34dfa7c7f848c12232c744150f79661c4c6..bb45b8a4e3bc5888ad37dfa6ed42f3c9a3e428ec 100644 (file)
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -32,7 +32,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 {
        auto &st = pm.st_ice40_dsp;
 
-#if 0
+#if 1
        log("\n");
        log("ffA:    %s\n", log_id(st.ffA, "--"));
        log("ffB:    %s\n", log_id(st.ffB, "--"));
@@ -66,10 +66,14 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
                return;
        }
 
-       log("  replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
+       Cell *cell = st.mul;
+       if (cell->type == "$mul") {
+               log("  replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
 
-       Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
-       pm.module->swap_names(cell, st.mul);
+               cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
+               pm.module->swap_names(cell, st.mul);
+       }
+       else log_assert(cell->type == "\\SB_MAC16");
 
        // SB_MAC16 Input Interface
        SigSpec A = st.sigA;
@@ -220,15 +224,18 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
        cell->setParam("\\A_SIGNED", st.mul->getParam("\\A_SIGNED").as_bool());
        cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
 
-       pm.autoremove(st.mul);
+       if (cell != st.mul)
+               pm.autoremove(st.mul);
+       else
+               pm.blacklist(st.mul);
        pm.autoremove(st.ffH);
        pm.autoremove(st.addAB);
        if (st.ffO_lo) {
-                       SigSpec O = st.sigO.extract(0,st.ffO_lo->getParam("\\WIDTH").as_int());
+                       SigSpec O = st.sigO.extract(0,std::min(16,st.ffO_lo->getParam("\\WIDTH").as_int()));
                        st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
        }
        if (st.ffO_hi) {
-                       SigSpec O = st.sigO.extract(16,st.ffO_hi->getParam("\\WIDTH").as_int());
+                       SigSpec O = st.sigO.extract_end(16);
                        st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
        }
 }

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 8b1ac25631698bdc7e59fff16d2776b1c148f4b8..1a62c7bdacdd77edcc743d28705f67afa80d3c8e 100644 (file)
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -2,18 +2,27 @@ pattern ice40_dsp
 
 state <SigBit> clock
 state <bool> clock_pol
-state <SigSpec> sigA sigB sigCD sigH sigO
+state <SigSpec> sigA sigB sigCD sigH sigO sigOused
 state <Cell*> addAB muxAB
 
 match mul
-       select mul->type.in($mul, $__MUL16X16)
+       select mul->type.in($mul, \SB_MAC16)
        select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
-       select GetSize(mul->getPort(\Y)) > 10
 endmatch
 
+code sigH
+       if (mul->type == $mul)
+               sigH = mul->getPort(\Y);
+       else if (mul->type == \SB_MAC16)
+               sigH = mul->getPort(\O);
+       else log_abort();
+       if (GetSize(sigH) <= 10)
+               reject;
+endcode
+
 match ffA
-                           // TODO: Support $dffe too by checking if all enable signals are identical
        select ffA->type.in($dff)
+       filter mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
        filter !port(mul, \A).remove_const().empty()
        filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set())
        optional
@@ -23,9 +32,9 @@ code sigA clock clock_pol
        sigA = port(mul, \A);
 
        if (ffA) {
-        for (auto b : port(ffA, \Q))
-            if (b.wire->get_bool_attribute(\keep))
-                reject;
+               for (auto b : port(ffA, \Q))
+                       if (b.wire->get_bool_attribute(\keep))
+                               reject;
 
                clock = port(ffA, \CLK).as_bit();
                clock_pol = param(ffA, \CLK_POLARITY).as_bool();
@@ -36,6 +45,7 @@ endcode
 
 match ffB
        select ffB->type.in($dff)
+       filter mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
        filter !port(mul, \B).remove_const().empty()
        filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set())
        optional
@@ -45,9 +55,9 @@ code sigB clock clock_pol
        sigB = port(mul, \B);
 
        if (ffB) {
-        for (auto b : port(ffB, \Q))
-            if (b.wire->get_bool_attribute(\keep))
-                reject;
+               for (auto b : port(ffB, \Q))
+                       if (b.wire->get_bool_attribute(\keep))
+                               reject;
 
                SigBit c = port(ffB, \CLK).as_bit();
                bool cp = param(ffB, \CLK_POLARITY).as_bool();
@@ -65,19 +75,20 @@ endcode
 match ffH
        select ffH->type.in($dff)
        select nusers(port(ffH, \D)) == 2
-       index <SigSpec> port(ffH, \D) === port(mul, \Y)
+       index <SigSpec> port(ffH, \D) === sigH
+       // Ensure pipeline register is not already used
+       filter mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
        optional
 endmatch
 
 code sigH sigO clock clock_pol
-       sigH = port(mul, \Y);
        sigO = sigH;
 
        if (ffH) {
                sigH = port(ffH, \Q);
-        for (auto b : sigH)
-            if (b.wire->get_bool_attribute(\keep))
-                reject;
+               for (auto b : sigH)
+                       if (b.wire->get_bool_attribute(\keep))
+                               reject;
 
                sigO = sigH;
 
@@ -119,6 +130,13 @@ code addAB sigCD sigO
                 sigCD.extend_u0(32, param(addAB, \A_SIGNED).as_bool());
        }
        if (addAB) {
+               if (mul->type == \SB_MAC16) {
+                       // Ensure that adder is not used
+                       if (param(mul, \TOPOUTPUT_SELECT).as_int() != 3 ||
+                                       param(mul, \BOTOUTPUT_SELECT).as_int() != 3)
+                               reject;
+               }
+
                int natural_mul_width = GetSize(sigA) + GetSize(sigB);
                int actual_mul_width = GetSize(sigH);
                int actual_acc_width = GetSize(sigO);
@@ -154,28 +172,49 @@ code muxAB
                muxAB = muxB;
 endcode
 
+// Extract the bits of P that actually have a consumer
+// (as opposed to being a dummy)
+code sigOused
+       for (int i = 0; i < GetSize(sigO); i++)
+               if (!sigO[i].wire || nusers(sigO[i]) == 1)
+                       sigOused.append(State::Sx);
+               else
+                       sigOused.append(sigO[i]);
+endcode
+
 match ffO_lo
        select ffO_lo->type.in($dff)
-       filter GetSize(sigO) >= param(ffO_lo, \WIDTH).as_int()
-       filter nusers(sigO.extract(0,param(ffO_lo, \WIDTH).as_int())) == 2
-       filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,param(ffO_lo, \WIDTH).as_int()).to_sigbit_set())
+       filter nusers(sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()))) == 2
+       filter includes(port(ffO_lo, \D).to_sigbit_set(), sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int())).remove_const().to_sigbit_set())
        optional
 endmatch
 
 match ffO_hi
        select ffO_hi->type.in($dff)
-       filter GetSize(sigO) >= 16+param(ffO_hi, \WIDTH).as_int()
-       filter nusers(sigO.extract(16,param(ffO_hi, \WIDTH).as_int())) == 2
-       filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,param(ffO_hi, \WIDTH).as_int()).to_sigbit_set())
+       filter GetSize(sigOused) > 16
+       filter nusers(sigOused.extract_end(16)) == 2
+       filter includes(port(ffO_hi, \D).to_sigbit_set(), sigOused.extract_end(16).remove_const().to_sigbit_set())
        optional
 endmatch
 
 code clock clock_pol sigO sigCD
        if (ffO_lo || ffO_hi) {
+               if (mul->type == \SB_MAC16) {
+                       // Ensure that register is not already used
+                       if (param(mul, \TOPOUTPUT_SELECT).as_int() == 1 ||
+                                       param(mul, \BOTOUTPUT_SELECT).as_int() == 1)
+                               reject;
+
+                       // Ensure that OLOADTOP/OLOADBOT is unused or zero
+                       if ((mul->hasPort(\OLOADTOP) && !port(mul, \OLOADTOP).is_fully_zero())
+                               || (mul->hasPort(\OLOADBOT) && !port(mul, \OLOADBOT).is_fully_zero()))
+                               reject;
+               }
+
                if (ffO_lo) {
-            for (auto b : port(ffO_lo, \Q))
-                if (b.wire->get_bool_attribute(\keep))
-                    reject;
+                       for (auto b : port(ffO_lo, \Q))
+                               if (b.wire->get_bool_attribute(\keep))
+                                       reject;
 
                        SigBit c = port(ffO_lo, \CLK).as_bit();
                        bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
@@ -186,14 +225,13 @@ code clock clock_pol sigO sigCD
                        clock = c;
                        clock_pol = cp;
 
-                       if (port(ffO_lo, \Q) != sigO.extract(0,param(ffO_lo, \WIDTH).as_int()))
-                               sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
+                       sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
                }
 
                if (ffO_hi) {
-            for (auto b : port(ffO_hi, \Q))
-                if (b.wire->get_bool_attribute(\keep))
-                    reject;
+                       for (auto b : port(ffO_hi, \Q))
+                               if (b.wire->get_bool_attribute(\keep))
+                                       reject;
 
                        SigBit c = port(ffO_hi, \CLK).as_bit();
                        bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
@@ -204,8 +242,7 @@ code clock clock_pol sigO sigCD
                        clock = c;
                        clock_pol = cp;
 
-                       if (port(ffO_hi, \Q) != sigO.extract(16,param(ffO_hi, \WIDTH).as_int()))
-                               sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
+                       sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
                }
 
                // Loading value into output register is not

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 6fd1207faebc8babb440906779ec90e0051a1e67..8abae93163951b9a2c9ac6bb66bcaeab7a3c9a80 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -44,7 +44,7 @@ code clock
 endcode
 
 // Extract the bits of P that actually have a consumer
-// (as opposed to being a sign extension)
+// (as opposed to being a dummy)
 code sigPused
        SigSpec P = port(dsp, \P);
        int i;

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index d258d5a5d901c3753da7c3fb1618bf479bfc5fea..b0eadab44f5f1ef059bb27bedc02a3c51d7dc45c 100644 (file)
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -28,6 +28,7 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box))

diff --git a/techlibs/ice40/dsp_map.v b/techlibs/ice40/dsp_map.v
new file mode 100644 (file)
index 0000000..06fa739
--- /dev/null
+++ b/techlibs/ice40/dsp_map.v
@@ -0,0 +1,34 @@
+module \$__MUL16X16 (input [15:0] A, input [15:0] B, output [31:0] Y);
+       parameter A_SIGNED = 0;
+       parameter B_SIGNED = 0;
+       parameter A_WIDTH = 0;
+       parameter B_WIDTH = 0;
+       parameter Y_WIDTH = 0;
+
+       SB_MAC16 #(
+               .NEG_TRIGGER(1'b0),
+               .C_REG(1'b0),
+               .A_REG(1'b0),
+               .B_REG(1'b0),
+               .D_REG(1'b0),
+               .TOP_8x8_MULT_REG(1'b0),
+               .BOT_8x8_MULT_REG(1'b0),
+               .PIPELINE_16x16_MULT_REG1(1'b0),
+               .PIPELINE_16x16_MULT_REG2(1'b0),
+               .TOPOUTPUT_SELECT(2'b11),
+               .TOPADDSUB_LOWERINPUT(2'b0),
+               .TOPADDSUB_UPPERINPUT(1'b0),
+               .TOPADDSUB_CARRYSELECT(2'b0),
+               .BOTOUTPUT_SELECT(2'b11),
+               .BOTADDSUB_LOWERINPUT(2'b0),
+               .BOTADDSUB_UPPERINPUT(1'b0),
+               .BOTADDSUB_CARRYSELECT(2'b0),
+               .MODE_8x8(1'b0),
+               .A_SIGNED(A_SIGNED),
+               .B_SIGNED(B_SIGNED)
+       ) _TECHMAP_REPLACE_ (
+               .A(A),
+               .B(B),
+               .O(Y),
+       );
+endmodule

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 09759f359136e12fce5eed6190f2c3208b2dc817..9c3670c7cb31e4b9a729afe1fc46a352c1030b28 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -266,7 +266,7 @@ struct SynthIce40Pass : public ScriptPass
                        run("opt_expr");
                        run("opt_clean");
                        if (help_mode || dsp) {
-                               run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
+                               run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
                                run("opt_expr -fine", "               (if -dsp)");
                                run("ice40_dsp", "                    (if -dsp)");
                                run("chtype -set $mul t:$__soft_mul","(if -dsp)");