Signed-off-by: Clifford Wolf <clifford@clifford.at>
--- /dev/null
+/fib_cover
+/fib_prove
+/fib_live
/wolf_goat_cabbage
-/primegen
+/primegen_primegen
+/primegen_primes_pass
+/primegen_primes_fail
+[tasks]
+primegen
+primes_fail
+primes_pass
+
[options]
mode cover
depth 1
+primes_fail: expect fail
[engines]
-smtbmc --dumpsmt2 --stbv z3
+smtbmc --dumpsmt2 --progress --stbv z3
[script]
read_verilog -formal primegen.v
-prep -top primegen
+primes_fail: chparam -set offset 7 primes
+primegen: prep -top primegen
+~primegen: prep -top primes
[files]
primegen.v
cover(1);
end
endmodule
+
+module primes;
+ parameter [8:0] offset = 500;
+ wire [8:0] prime1 = $anyconst;
+ wire [9:0] prime2 = prime1 + offset;
+ wire [4:0] factor = $allconst;
+
+ always @* begin
+ if (1 < factor && factor < prime1)
+ assume((prime1 % factor) != 0);
+ if (1 < factor && factor < prime2)
+ assume((prime2 % factor) != 0);
+ assume(1 < prime1);
+ cover(1);
+ end
+endmodule