+2018-05-04 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * common/config/rs6000/rs6000-common.c (rs6000_handle_option): Remove
+ Xilinx FP support.
+ * config.gcc (powerpc-xilinx-eabi*): Remove.
+ * config/rs6000/predicates.md (easy_fp_constant): Remove Xilinx FP
+ support.
+ (fusion_addis_mem_combo_load): Ditto.
+ * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Remove Xilinx
+ FP support.
+ (rs6000_cpu_cpp_builtins): Ditto.
+ * config/rs6000/rs6000-linux.c
+ (rs6000_linux_float_exceptions_rounding_supported_p): Ditto.
+ * config/rs6000/rs6000-opts.h (enum fpu_type_t): Delete.
+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Remove Xilinx FP
+ support.
+ (rs6000_setup_reg_addr_masks): Ditto.
+ (rs6000_init_hard_regno_mode_ok): Ditto.
+ (rs6000_option_override_internal): Ditto.
+ (legitimate_lo_sum_address_p): Ditto.
+ (rs6000_legitimize_address): Ditto.
+ (rs6000_legitimize_reload_address): Ditto.
+ (rs6000_legitimate_address_p): Ditto.
+ (abi_v4_pass_in_fpr): Ditto.
+ (setup_incoming_varargs): Ditto.
+ (rs6000_gimplify_va_arg): Ditto.
+ (rs6000_split_multireg_move): Ditto.
+ (rs6000_savres_strategy): Ditto.
+ (rs6000_emit_prologue_components): Ditto.
+ (rs6000_emit_epilogue_components): Ditto.
+ (rs6000_emit_prologue): Ditto.
+ (rs6000_emit_epilogue): Ditto.
+ (rs6000_elf_file_end): Ditto.
+ (rs6000_function_value): Ditto.
+ (rs6000_libcall_value): Ditto.
+ * config/rs6000/rs6000.h: Ditto.
+ (TARGET_MINMAX_SF, TARGET_MINMAX_DF): Delete, merge to ...
+ (TARGET_MINMAX): ... this. New.
+ (TARGET_SF_FPR, TARGET_DF_FPR, TARGET_SF_INSN, TARGET_DF_INSN): Delete.
+ * config/rs6000/rs6000.md: Remove Xilinx FP support.
+ (*movsi_internal1_single): Delete.
+ * config/rs6000/rs6000.opt (msingle-float, mdouble-float, msimple-fpu,
+ mfpu=, mxilinx-fpu): Delete.
+ * config/rs6000/singlefp.h: Delete.
+ * config/rs6000/sysv4.h: Remove Xilinx FP support.
+ * config/rs6000/t-rs6000: Ditto.
+ * config/rs6000/t-xilinx: Delete.
+ * gcc/config/rs6000/titan.md: Adjust for fp_type removal.
+ * gcc/config/rs6000/vsx.md: Remove Xilinx FP support.
+ (VStype_simple): Delete.
+ (VSfptype_simple, VSfptype_mul, VSfptype_div, VSfptype_sqrt): Delete.
+ * config/rs6000/xfpu.h: Delete.
+ * config/rs6000/xfpu.md: Delete.
+ * config/rs6000/xilinx.h: Delete.
+ * config/rs6000/xilinx.opt: Delete.
+ * gcc/doc/invoke.texi (RS/6000 and PowerPC Options): Remove
+ -msingle-float, -mdouble-float, -msimple-fpu, -mfpu=, and -mxilinx-fpu.
+
2018-05-04 Tom de Vries <tom@codesourcery.com>
PR libgomp/85639
const struct cl_decoded_option *decoded,
location_t loc)
{
- enum fpu_type_t fpu_type = FPU_NONE;
char *p, *q;
size_t code = decoded->opt_index;
const char *arg = decoded->arg;
}
break;
- case OPT_msingle_float:
- if (!TARGET_SINGLE_FPU)
- warning_at (loc, 0,
- "-msingle-float option equivalent to -mhard-float");
- /* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */
- opts->x_rs6000_double_float = 0;
- opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
- opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
- break;
-
- case OPT_mdouble_float:
- /* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */
- opts->x_rs6000_single_float = 1;
- opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
- opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
- break;
-
- case OPT_msimple_fpu:
- if (!TARGET_SINGLE_FPU)
- warning_at (loc, 0, "-msimple-fpu option ignored");
- break;
-
- case OPT_mhard_float:
- /* -mhard_float implies -msingle-float and -mdouble-float. */
- opts->x_rs6000_single_float = opts->x_rs6000_double_float = 1;
- break;
-
- case OPT_msoft_float:
- /* -msoft_float implies -mnosingle-float and -mnodouble-float. */
- opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0;
- break;
-
- case OPT_mfpu_:
- fpu_type = (enum fpu_type_t) value;
- if (fpu_type != FPU_NONE)
- {
- /* If -mfpu is not none, then turn off SOFT_FLOAT, turn on
- HARD_FLOAT. */
- opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
- opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
- opts->x_rs6000_xilinx_fpu = 1;
- if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL)
- opts->x_rs6000_single_float = 1;
- if (fpu_type == FPU_DF_LITE || fpu_type == FPU_DF_FULL)
- opts->x_rs6000_single_float = opts->x_rs6000_double_float = 1;
- if (fpu_type == FPU_SF_LITE || fpu_type == FPU_DF_LITE)
- opts->x_rs6000_simple_fpu = 1;
- }
- else
- {
- /* -mfpu=none is equivalent to -msoft-float. */
- opts->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
- opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
- opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0;
- }
- break;
-
case OPT_mrecip:
opts->x_rs6000_recip_name = (value) ? "default" : "none";
break;
tmake_file="rs6000/t-fprules rs6000/t-ppcendian rs6000/t-ppccomm"
use_gcc_stdint=wrap
;;
-powerpc-xilinx-eabi*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/singlefp.h rs6000/xfpu.h rs6000/xilinx.h"
- extra_options="${extra_options} rs6000/sysv4.opt rs6000/xilinx.opt"
- tmake_file="rs6000/t-fprules rs6000/t-ppcgas rs6000/t-ppccomm rs6000/t-xilinx"
- use_gcc_stdint=wrap
- ;;
powerpc-*-eabi*)
tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h"
extra_options="${extra_options} rs6000/sysv4.opt"
return 0;
/* Consider all constants with -msoft-float to be easy. */
- if ((TARGET_SOFT_FLOAT
- || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
- && mode != DImode)
+ if (TARGET_SOFT_FLOAT && mode != DImode)
return 1;
/* 0.0D is not all zero bits. */
DFmode in 32-bit if -msoft-float since it splits into two separate
instructions. */
case E_DFmode:
- if ((!TARGET_POWERPC64 && !TARGET_DF_FPR) || !TARGET_P9_FUSION)
+ if ((!TARGET_POWERPC64 && !TARGET_HARD_FLOAT) || !TARGET_P9_FUSION)
return 0;
break;
into two separate instructions. Do allow fusion if we have hardware
floating point. */
case E_DFmode:
- if (!TARGET_POWERPC64 && !TARGET_DF_FPR)
+ if (!TARGET_POWERPC64 && !TARGET_HARD_FLOAT)
return 0;
break;
the following conditions:
1. The operating system does not support saving of AltiVec
registers (OS_MISSING_ALTIVEC).
- 2. If any of the options TARGET_HARD_FLOAT, TARGET_SINGLE_FLOAT,
- or TARGET_DOUBLE_FLOAT are turned off. Hereafter, the
+ 2. If the option TARGET_HARD_FLOAT is turned off. Hereafter, the
OPTION_MASK_VSX flag is considered to have been turned off
explicitly.
3. If TARGET_AVOID_XFORM is turned on explicitly at the outermost
cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand;
}
}
- if (!TARGET_HARD_FLOAT || !TARGET_DOUBLE_FLOAT)
+ if (!TARGET_HARD_FLOAT)
builtin_define ("_SOFT_DOUBLE");
/* Used by lwarx/stwcx. errata work-around. */
if (rs6000_cpu == PROCESSOR_PPC405)
|| DEFAULT_ABI == ABI_ELFv2
|| (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
builtin_define ("__STRUCT_PARM_ALIGN__=16");
-
- /* Generate defines for Xilinx FPU. */
- if (rs6000_xilinx_fpu)
- {
- builtin_define ("_XFPU");
- if (rs6000_single_float && ! rs6000_double_float)
- {
- if (rs6000_simple_fpu)
- builtin_define ("_XFPU_SP_LITE");
- else
- builtin_define ("_XFPU_SP_FULL");
- }
- if (rs6000_double_float)
- {
- if (rs6000_simple_fpu)
- builtin_define ("_XFPU_DP_LITE");
- else
- builtin_define ("_XFPU_DP_FULL");
- }
- }
}
\f
if (OPTION_GLIBC)
return true;
else
- return TARGET_DF_INSN;
+ return TARGET_HARD_FLOAT;
}
};
-/* FP processor type. */
-enum fpu_type_t
-{
- FPU_NONE, /* No FPU */
- FPU_SF_LITE, /* Limited Single Precision FPU */
- FPU_DF_LITE, /* Limited Double Precision FPU */
- FPU_SF_FULL, /* Full Single Precision FPU */
- FPU_DF_FULL /* Full Double Single Precision FPU */
-};
-
-
/* Types of costly dependences. */
enum rs6000_dependence_cost
{
if (rs6000_darwin64_abi)
fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
- fprintf (stderr, DEBUG_FMT_S, "single_float",
- (TARGET_SINGLE_FLOAT ? "true" : "false"));
-
- fprintf (stderr, DEBUG_FMT_S, "double_float",
- (TARGET_DOUBLE_FLOAT ? "true" : "false"));
-
fprintf (stderr, DEBUG_FMT_S, "soft_float",
(TARGET_SOFT_FLOAT ? "true" : "false"));
case E_DFmode:
case E_DDmode:
- if (TARGET_DF_INSN)
+ if (TARGET_HARD_FLOAT)
addr_mask |= RELOAD_REG_PRE_MODIFY;
break;
}
wK - Altivec register if QImode/HImode are allowed in VSX registers. */
if (TARGET_HARD_FLOAT)
- rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
-
- if (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
- rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
+ {
+ rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
+ }
if (TARGET_VSX)
{
reg_addr[DImode].fused_toc = true;
if (TARGET_HARD_FLOAT)
{
- if (TARGET_SINGLE_FLOAT)
- reg_addr[SFmode].fused_toc = true;
- if (TARGET_DOUBLE_FLOAT)
- reg_addr[DFmode].fused_toc = true;
+ reg_addr[SFmode].fused_toc = true;
+ reg_addr[DFmode].fused_toc = true;
}
}
if (TARGET_VSX)
{
const char *msg = NULL;
- if (!TARGET_HARD_FLOAT || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
+ if (!TARGET_HARD_FLOAT)
{
if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
msg = N_("-mvsx requires hardware floating point");
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
- if (main_target_opt)
- {
- if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
- error ("target attribute or pragma changes single precision floating "
- "point");
- if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
- error ("target attribute or pragma changes double precision floating "
- "point");
- }
-
rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
&& rs6000_tune != PROCESSOR_POWER5
&& rs6000_tune != PROCESSOR_POWER6
targetm.expand_builtin_va_start = NULL;
}
- /* Set up single/double float flags.
- If TARGET_HARD_FLOAT is set, but neither single or double is set,
- then set both flags. */
- if (TARGET_HARD_FLOAT && rs6000_single_float == 0 && rs6000_double_float == 0)
- rs6000_single_float = rs6000_double_float = 1;
-
/* If not explicitly specified via option, decide whether to generate indexed
load/store instructions. A value of -1 indicates that the
initial value of this variable has not been overwritten. During
return false;
if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
&& !(/* ??? Assume floating point reg based on mode? */
- TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
- && (mode == DFmode || mode == DDmode)))
+ TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
return false;
return CONSTANT_P (x) || large_toc_ok;
&& GET_MODE_NUNITS (mode) == 1
&& (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
|| (/* ??? Assume floating point reg based on mode? */
- (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
- && (mode == DFmode || mode == DDmode)))
+ TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
&& !avoiding_indexed_address_p (mode))
{
return gen_rtx_PLUS (Pmode, XEXP (x, 0),
&& GET_MODE_NUNITS (mode) == 1
&& (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
|| (/* ??? Assume floating point reg based on mode? */
- (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
- && (mode == DFmode || mode == DDmode))))
+ TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode))))
{
rtx reg = gen_reg_rtx (Pmode);
if (TARGET_ELF)
&& mode != PTImode
&& (mode != DImode || TARGET_POWERPC64)
&& ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
- || (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)))
+ || TARGET_HARD_FLOAT))
{
#if TARGET_MACHO
if (flag_pic)
if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
return 1;
if (!FLOAT128_2REG_P (mode)
- && ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
+ && (TARGET_HARD_FLOAT
|| TARGET_POWERPC64
|| (mode != DFmode && mode != DDmode))
&& (TARGET_POWERPC64 || mode != DImode)
{
if (!TARGET_HARD_FLOAT)
return false;
- if (TARGET_DOUBLE_FLOAT && mode == DFmode)
+ if (mode == DFmode)
return true;
- if (TARGET_SINGLE_FLOAT && mode == SFmode && named)
+ if (mode == SFmode && named)
return true;
/* ABI_V4 passes complex IBM long double in 8 gprs.
Stupid, but we can't change the ABI now. */
fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
fregno++, off += UNITS_PER_FP_WORD, nregs++)
{
- mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
- ? DFmode : SFmode,
+ mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
plus_constant (Pmode, save_area, off));
MEM_NOTRAP_P (mem) = 1;
set_mem_alias_set (mem, set);
set_mem_align (mem, GET_MODE_ALIGNMENT (
- (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
- ? DFmode : SFmode));
+ TARGET_HARD_FLOAT ? DFmode : SFmode));
emit_move_insn (mem, gen_rtx_REG (
- (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
- ? DFmode : SFmode, fregno));
+ TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
}
emit_label (lab);
/* FP args go in FP registers, if present. */
reg = fpr;
n_reg = (size + 7) / 8;
- sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
- sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
+ sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
+ sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
if (mode != SFmode && mode != SDmode)
align = 8;
}
mode = GET_MODE (dst);
nregs = hard_regno_nregs (reg, mode);
if (FP_REGNO_P (reg))
- reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
- ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
+ reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
+ (TARGET_HARD_FLOAT ? DFmode : SFmode);
else if (ALTIVEC_REGNO_P (reg))
reg_mode = V16QImode;
else
if (info->first_gp_reg_save == 32)
strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
- if (info->first_fp_reg_save == 64
- /* The out-of-line FP routines use double-precision stores;
- we can't use those routines if we don't have such stores. */
- || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT))
+ if (info->first_fp_reg_save == 64)
strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
machine_mode reg_mode = Pmode;
int reg_size = TARGET_32BIT ? 4 : 8;
- machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
- ? DFmode : SFmode;
+ machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
int fp_reg_size = 8;
/* Prologue for LR. */
machine_mode reg_mode = Pmode;
int reg_size = TARGET_32BIT ? 4 : 8;
- machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
- ? DFmode : SFmode;
+ machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
int fp_reg_size = 8;
/* Epilogue for the FPRs. */
rs6000_stack_t *info = rs6000_stack_info ();
machine_mode reg_mode = Pmode;
int reg_size = TARGET_32BIT ? 4 : 8;
- machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
- ? DFmode : SFmode;
+ machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
int fp_reg_size = 8;
rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
rtx frame_reg_rtx = sp_reg_rtx;
properly. */
for (i = 0; i < 64 - info->first_fp_reg_save; i++)
RTVEC_ELT (p, j++)
- = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
- ? DFmode : SFmode,
+ = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
info->first_fp_reg_save + i),
frame_reg_rtx,
info->fp_save_offset + frame_off + 8 * i);
rtx cr_save_reg = NULL_RTX;
machine_mode reg_mode = Pmode;
int reg_size = TARGET_32BIT ? 4 : 8;
- machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
- ? DFmode : SFmode;
+ machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
int fp_reg_size = 8;
int i;
bool exit_func;
}
for (i = 0; info->first_fp_reg_save + i <= 63; i++)
{
- rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
- ? DFmode : SFmode),
+ rtx reg = gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
info->first_fp_reg_save + i);
RTVEC_ELT (p, j++)
= gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
{
int fp;
- if (TARGET_DF_FPR)
+ if (TARGET_HARD_FLOAT)
fp = 1;
- else if (TARGET_SF_FPR)
- fp = 3;
else
fp = 2;
if (rs6000_passes_long_double)
/* _Decimal128 must use an even/odd register pair. */
regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
- && !FLOAT128_VECTOR_P (mode)
- && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
+ && !FLOAT128_VECTOR_P (mode))
regno = FP_ARG_RETURN;
else if (TREE_CODE (valtype) == COMPLEX_TYPE
&& targetm.calls.split_complex_arg)
if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
/* _Decimal128 must use an even/odd register pair. */
regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
- else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode)
- && TARGET_HARD_FLOAT
- && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
+ else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && TARGET_HARD_FLOAT)
regno = FP_ARG_RETURN;
/* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
return register is used in both cases, and we won't see V2DImode/V2DFmode
#define TARGET_DEFAULT (MASK_MULTIPLE)
-/* FPU operations supported.
- Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
- also test TARGET_HARD_FLOAT. */
-#define TARGET_SINGLE_FLOAT 1
-#define TARGET_DOUBLE_FLOAT 1
-#define TARGET_SINGLE_FPU 0
-#define TARGET_SIMPLE_FPU 0
-#define TARGET_XILINX_FPU 0
-
/* Define generic processor types based upon current deployment. */
#define PROCESSOR_COMMON PROCESSOR_PPC601
#define PROCESSOR_POWERPC PROCESSOR_PPC604
#endif
/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
- Enable 32-bit fcfid's on any of the switches for newer ISA machines or
- XILINX. */
+ Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
#define TARGET_FCFID (TARGET_POWERPC64 \
|| TARGET_PPC_GPOPT /* 970/power4 */ \
|| TARGET_POPCNTB /* ISA 2.02 */ \
|| TARGET_CMPB /* ISA 2.05 */ \
- || TARGET_POPCNTD /* ISA 2.06 */ \
- || TARGET_XILINX_FPU)
+ || TARGET_POPCNTD) /* ISA 2.06 */
#define TARGET_FCTIDZ TARGET_FCFID
#define TARGET_STFIWX TARGET_PPC_GFXOPT
/* ISA 3.0 has new min/max functions that don't need fast math that are being
phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
answers if the arguments are not in the normal range. */
-#define TARGET_MINMAX_SF (TARGET_SF_FPR && TARGET_PPC_GFXOPT \
- && (TARGET_P9_MINMAX || !flag_trapping_math))
-
-#define TARGET_MINMAX_DF (TARGET_DF_FPR && TARGET_PPC_GFXOPT \
- && (TARGET_P9_MINMAX || !flag_trapping_math))
+#define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
+ && (TARGET_P9_MINMAX || !flag_trapping_math))
/* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
|| rs6000_cpu == PROCESSOR_PPC8548)
-/* Whether SF/DF operations are supported by the normal floating point unit
- (or the vector/scalar unit). */
-#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT)
-#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
-
-/* Whether SF/DF operations are supported by any hardware. */
-#define TARGET_SF_INSN TARGET_SF_FPR
-#define TARGET_DF_INSN TARGET_DF_FPR
-
/* Which machine supports the various reciprocal estimate instructions. */
-#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
- && TARGET_SINGLE_FLOAT)
+#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
-#define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
+#define TARGET_FRE (TARGET_HARD_FLOAT \
&& (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
- && TARGET_PPC_GFXOPT && TARGET_SINGLE_FLOAT)
+ && TARGET_PPC_GFXOPT)
-#define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
+#define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
&& (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
/* Conditions to allow TOC fusion for loading/storing integers. */
&& TARGET_TOC_FUSION \
&& (TARGET_CMODEL != CMODEL_SMALL) \
&& TARGET_POWERPC64 \
- && TARGET_HARD_FLOAT \
- && TARGET_SINGLE_FLOAT \
- && TARGET_DOUBLE_FLOAT)
+ && TARGET_HARD_FLOAT)
/* Macro to say whether we can do optimizations where we need to do parts of
the calculation in 64-bit GPRs and then is transfered to the vector
;; Is copying of this instruction disallowed?
(define_attr "cannot_copy" "no,yes" (const_string "no"))
-;; Define floating point instruction sub-types for use with Xfpu.md
-(define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
-
;; Length (in bytes).
; '(pc)' in the following doesn't include the instruction itself; it is
; calculated as if the instruction had zero size.
(include "power8.md")
(include "power9.md")
(include "cell.md")
-(include "xfpu.md")
(include "a2.md")
(include "titan.md")
; Any hardware-supported floating-point mode
(define_mode_iterator FP [
- (SF "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT")
- (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
+ (SF "TARGET_HARD_FLOAT")
+ (DF "TARGET_HARD_FLOAT")
(TF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
(IF "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128")
(KF "TARGET_FLOAT128_TYPE")
; Any fma capable floating-point mode.
(define_mode_iterator FMA_F [
- (SF "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT")
- (DF "(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
- || VECTOR_UNIT_VSX_P (DFmode)")
+ (SF "TARGET_HARD_FLOAT")
+ (DF "TARGET_HARD_FLOAT || VECTOR_UNIT_VSX_P (DFmode)")
(V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
(V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
(KF "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (KFmode)")
; SF/DF constraint for arithmetic on altivec registers
(define_mode_attr Fa [(SF "wu") (DF "wv")])
-; s/d suffix for things like fp_addsub_s/fp_addsub_d
+; s/d suffix for things like sdiv/ddiv
(define_mode_attr Fs [(SF "s") (DF "d")])
; FRE/FRES support
(define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
(DF "TARGET_FCFID")])
-(define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
- (DF "TARGET_DOUBLE_FLOAT")])
-
;; Mode iterator for logical operations on 128-bit types
(define_mode_iterator BOOL_128 [TI
PTI
(define_expand "abs<mode>2"
[(set (match_operand:SFDF 0 "gpc_reg_operand")
(abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))]
- "TARGET_<MODE>_INSN"
+ "TARGET_HARD_FLOAT"
"")
(define_insn "*abs<mode>2_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
(abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
- "TARGET_<MODE>_FPR"
+ "TARGET_HARD_FLOAT"
"@
fabs %0,%1
xsabsdp %x0,%x1"
- [(set_attr "type" "fpsimple")
- (set_attr "fp_type" "fp_addsub_<Fs>")])
+ [(set_attr "type" "fpsimple")])
(define_insn "*nabs<mode>2_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
(neg:SFDF
(abs:SFDF
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
- "TARGET_<MODE>_FPR"
+ "TARGET_HARD_FLOAT"
"@
fnabs %0,%1
xsnabsdp %x0,%x1"
- [(set_attr "type" "fpsimple")
- (set_attr "fp_type" "fp_addsub_<Fs>")])
+ [(set_attr "type" "fpsimple")])
(define_expand "neg<mode>2"
[(set (match_operand:SFDF 0 "gpc_reg_operand")
(neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))]
- "TARGET_<MODE>_INSN"
+ "TARGET_HARD_FLOAT"
"")
(define_insn "*neg<mode>2_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
(neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
- "TARGET_<MODE>_FPR"
+ "TARGET_HARD_FLOAT"
"@
fneg %0,%1
xsnegdp %x0,%x1"
- [(set_attr "type" "fpsimple")
- (set_attr "fp_type" "fp_addsub_<Fs>")])
+ [(set_attr "type" "fpsimple")])
(define_expand "add<mode>3"
[(set (match_operand:SFDF 0 "gpc_reg_operand")
(plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
(match_operand:SFDF 2 "gpc_reg_operand")))]
- "TARGET_<MODE>_INSN"
+ "TARGET_HARD_FLOAT"
"")
(define_insn "*add<mode>3_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
(plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
- "TARGET_<MODE>_FPR"
+ "TARGET_HARD_FLOAT"
"@
fadd<Ftrad> %0,%1,%2
xsadd<Fvsx> %x0,%x1,%x2"
- [(set_attr "type" "fp")
- (set_attr "fp_type" "fp_addsub_<Fs>")])
+ [(set_attr "type" "fp")])
(define_expand "sub<mode>3"
[(set (match_operand:SFDF 0 "gpc_reg_operand")
(minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
(match_operand:SFDF 2 "gpc_reg_operand")))]
- "TARGET_<MODE>_INSN"
+ "TARGET_HARD_FLOAT"
"")
(define_insn "*sub<mode>3_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
(minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
- "TARGET_<MODE>_FPR"
+ "TARGET_HARD_FLOAT"
"@
fsub<Ftrad> %0,%1,%2
xssub<Fvsx> %x0,%x1,%x2"
- [(set_attr "type" "fp")
- (set_attr "fp_type" "fp_addsub_<Fs>")])
+ [(set_attr "type" "fp")])
(define_expand "mul<mode>3"
[(set (match_operand:SFDF 0 "gpc_reg_operand")
(mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
(match_operand:SFDF 2 "gpc_reg_operand")))]
- "TARGET_<MODE>_INSN"
+ "TARGET_HARD_FLOAT"
"")
(define_insn "*mul<mode>3_fpr"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
(mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
- "TARGET_<MODE>_FPR"
+ "TARGET_HARD_FLOAT"
"@
fmul<Ftrad> %0,%1,%2
xsmul<Fvsx> %x0,%x1,%x2"
- [(set_attr "type" "dmul")
- (set_attr "fp_type" "fp_mul_<Fs>")])
+ [(set_attr "type" "dmul")])
(define_expand "div<mode>3"
[(set (match_operand:SFDF 0 "gpc_reg_operand")
(div:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
(match_operand:SFDF 2 "gpc_reg_operand")))]
- "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
+ "TARGET_HARD_FLOAT"
{
if (RS6000_RECIP_AUTO_RE_P (<MODE>mode)
&& can_create_pseudo_p () && flag_finite_math_only
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
(div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
- "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
+ "TARGET_HARD_FLOAT"
"@
fdiv<Ftrad> %0,%1,%2
xsdiv<Fvsx> %x0,%x1,%x2"
- [(set_attr "type" "<Fs>div")
- (set_attr "fp_type" "fp_div_<Fs>")])
+ [(set_attr "type" "<Fs>div")])
(define_insn "*sqrt<mode>2_internal"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
(sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")))]
- "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
- && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
+ "TARGET_HARD_FLOAT && TARGET_PPC_GPOPT"
"@
fsqrt<Ftrad> %0,%1
xssqrt<Fvsx> %x0,%x1"
- [(set_attr "type" "<Fs>sqrt")
- (set_attr "fp_type" "fp_sqrt_<Fs>")])
+ [(set_attr "type" "<Fs>sqrt")])
(define_expand "sqrt<mode>2"
[(set (match_operand:SFDF 0 "gpc_reg_operand")
(sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))]
- "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
- && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
+ "TARGET_HARD_FLOAT && TARGET_PPC_GPOPT"
{
if (<MODE>mode == SFmode
&& TARGET_RECIP_PRECISION
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
(compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
- "TARGET_<MODE>_FPR"
+ "TARGET_HARD_FLOAT"
"@
fcmpu %0,%1,%2
xscmpudp %0,%x1,%x2"
(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand")
(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "TARGET_HARD_FLOAT"
{
if (HONOR_SNANS (SFmode))
operands[1] = force_reg (SFmode, operands[1]);
(define_insn_and_split "*extendsfdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wu,wb")
(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z,wY")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !HONOR_SNANS (SFmode)"
+ "TARGET_HARD_FLOAT && !HONOR_SNANS (SFmode)"
"@
#
fmr %0,%1
(define_insn "*extendsfdf2_snan"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f,wy")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && HONOR_SNANS (SFmode)"
+ "TARGET_HARD_FLOAT && HONOR_SNANS (SFmode)"
"@
frsp %0,%1
xsrsp %x0,%x1"
(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "TARGET_HARD_FLOAT"
"")
(define_insn "*truncdfsf2_fpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,ws")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "TARGET_HARD_FLOAT"
"@
frsp %0,%1
xsrsp %x0,%x1"
(match_dup 5))
(match_dup 3)
(match_dup 4)))]
- "TARGET_HARD_FLOAT && <TARGET_FLOAT>
+ "TARGET_HARD_FLOAT
&& ((TARGET_PPC_GFXOPT
&& !HONOR_NANS (<MODE>mode)
&& !HONOR_SIGNED_ZEROS (<MODE>mode))
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
UNSPEC_COPYSIGN))]
- "TARGET_<MODE>_FPR && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
+ "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
"@
fcpsgn %0,%2,%1
xscpsgndp %x0,%x2,%x1"
[(set (match_operand:SFDF 0 "gpc_reg_operand")
(fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
(match_operand:SFDF 2 "gpc_reg_operand")))]
- "TARGET_MINMAX_<MODE>"
+ "TARGET_MINMAX"
{
rs6000_emit_minmax (operands[0], <SMINMAX>, operands[1], operands[2]);
DONE;
[(set (match_operand:SFDF 0 "vsx_register_operand" "=<Fv>")
(fp_minmax:SFDF (match_operand:SFDF 1 "vsx_register_operand" "<Fv>")
(match_operand:SFDF 2 "vsx_register_operand" "<Fv>")))]
- "TARGET_VSX && TARGET_<MODE>_FPR"
+ "TARGET_VSX && TARGET_HARD_FLOAT"
{
return (TARGET_P9_MINMAX
? "xs<minmax>cdp %x0,%x1,%x2"
[(set (match_operand:SFDF 0 "gpc_reg_operand")
(fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
(match_operand:SFDF 2 "gpc_reg_operand")))]
- "!TARGET_VSX && TARGET_MINMAX_<MODE>"
+ "!TARGET_VSX && TARGET_MINMAX"
"#"
"&& 1"
[(const_int 0)]
(if_then_else:SFDF (match_operand 1 "comparison_operator")
(match_operand:SFDF 2 "gpc_reg_operand")
(match_operand:SFDF 3 "gpc_reg_operand")))]
- "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT"
+ "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
{
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
DONE;
(match_operand:SFDF2 4 "zero_fp_constant" "F"))
(match_operand:SFDF 2 "gpc_reg_operand" "<SFDF:rreg2>")
(match_operand:SFDF 3 "gpc_reg_operand" "<SFDF:rreg2>")))]
- "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT"
+ "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
"fsel %0,%1,%2,%3"
[(set_attr "type" "fp")])
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wK")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wK")]
UNSPEC_LFIWAX))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
+ "TARGET_HARD_FLOAT && TARGET_LFIWAX"
"@
lfiwax %0,%y1
lxsiwax %x0,%y1
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
(float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
(clobber (match_scratch:DI 2 "=wi"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
+ "TARGET_HARD_FLOAT && TARGET_LFIWAX
&& <SI_CONVERT_FP> && can_create_pseudo_p ()"
"#"
""
(sign_extend:DI
(match_operand:SI 1 "indexed_or_indirect_operand" "Z"))))
(clobber (match_scratch:DI 2 "=wi"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX && <SI_CONVERT_FP>"
+ "TARGET_HARD_FLOAT && TARGET_LFIWAX && <SI_CONVERT_FP>"
"#"
""
[(pc)]
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,wj,wJwK")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r,wJwK")]
UNSPEC_LFIWZX))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
+ "TARGET_HARD_FLOAT && TARGET_LFIWZX"
"@
lfiwzx %0,%y1
lxsiwzx %x0,%y1
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
(unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
(clobber (match_scratch:DI 2 "=wi"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
+ "TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
"#"
""
[(pc)]
(zero_extend:DI
(match_operand:SI 1 "indexed_or_indirect_operand" "Z"))))
(clobber (match_scratch:DI 2 "=wi"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
+ "TARGET_HARD_FLOAT && TARGET_LFIWZX && <SI_CONVERT_FP>"
"#"
""
[(pc)]
(clobber (match_dup 4))
(clobber (match_dup 5))
(clobber (match_dup 6))])]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "TARGET_HARD_FLOAT"
{
if (TARGET_LFIWAX && TARGET_FCFID)
{
(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
(clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
- "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "!TARGET_FCFID && TARGET_HARD_FLOAT"
"#"
""
[(pc)]
(define_expand "floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))]
- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
+ "TARGET_HARD_FLOAT
&& ((TARGET_FCFIDUS && TARGET_LFIWZX)
- || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
+ || (TARGET_FCFID
&& (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
{
if (TARGET_LFIWZX && TARGET_FCFIDUS)
(use (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "TARGET_HARD_FLOAT"
{
if (TARGET_LFIWZX && TARGET_FCFID)
{
(use (match_operand:DF 3 "gpc_reg_operand" "d"))
(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
- "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+ "!TARGET_FCFIDU && TARGET_HARD_FLOAT
&& !(TARGET_FCFID && TARGET_POWERPC64)"
"#"
""
(define_expand "fix_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand")
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))]
- "TARGET_HARD_FLOAT && <TARGET_FLOAT>"
+ "TARGET_HARD_FLOAT"
{
if (!(TARGET_P8_VECTOR && TARGET_DIRECT_MOVE))
{
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DI 2 "=d"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
- && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
- && TARGET_STFIWX && can_create_pseudo_p ()
+ "TARGET_HARD_FLOAT && TARGET_STFIWX && can_create_pseudo_p ()
&& !(TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)"
"#"
""
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+ "TARGET_HARD_FLOAT
&& !(TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)"
"#"
""
(define_expand "fix_trunc<mode>di2"
[(set (match_operand:DI 0 "gpc_reg_operand")
(fix:DI (match_operand:SFDF 1 "gpc_reg_operand")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID"
+ "TARGET_HARD_FLOAT && TARGET_FCFID"
"")
(define_insn "*fix_trunc<mode>di2_fctidz"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
(fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID"
+ "TARGET_HARD_FLOAT && TARGET_FCFID"
"@
fctidz %0,%1
xscvdpsxds %x0,%x1"
(define_expand "fixuns_trunc<mode>si2"
[(set (match_operand:SI 0 "gpc_reg_operand")
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))]
- "TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX"
+ "TARGET_HARD_FLOAT && TARGET_FCTIWUZ && TARGET_STFIWX"
{
if (!TARGET_P8_VECTOR)
{
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DI 2 "=d"))]
- "TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ
+ "TARGET_HARD_FLOAT && TARGET_FCTIWUZ
&& TARGET_STFIWX && can_create_pseudo_p ()
&& !TARGET_P8_VECTOR"
"#"
(define_insn "fixuns_trunc<mode>di2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
(unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCTIDUZ"
+ "TARGET_HARD_FLOAT && TARGET_FCTIDUZ"
"@
fctiduz %0,%1
xscvdpuxds %x0,%x1"
(unspec:DI [(fix:SI
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
UNSPEC_FCTIWZ))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "TARGET_HARD_FLOAT"
"@
fctiwz %0,%1
xscvdpsxws %x0,%x1"
(unspec:DI [(unsigned_fix:SI
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
UNSPEC_FCTIWUZ))]
- "TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ"
+ "TARGET_HARD_FLOAT && TARGET_FCTIWUZ"
"@
fctiwuz %0,%1
xscvdpuxws %x0,%x1"
(define_insn "*friz"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,ws"))))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRND
+ "TARGET_HARD_FLOAT && TARGET_FPRND
&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
"@
friz %0,%1
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
(clobber (match_scratch:DI 2 "=d"))
(clobber (match_scratch:DI 3 "=d"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+ "TARGET_HARD_FLOAT
&& <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
&& !TARGET_DIRECT_MOVE && can_create_pseudo_p ()"
"#"
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
(clobber (match_scratch:DI 2 "=d"))
(clobber (match_scratch:DI 3 "=d"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+ "TARGET_HARD_FLOAT
&& TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU && !TARGET_DIRECT_MOVE
&& can_create_pseudo_p ()"
"#"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
(unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FCTID))]
- "TARGET_<MODE>_FPR && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"fctid %0,%1"
[(set_attr "type" "fp")])
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
UNSPEC_FRIZ))]
- "TARGET_<MODE>_FPR && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"@
friz %0,%1
xsrdpiz %x0,%x1"
- [(set_attr "type" "fp")
- (set_attr "fp_type" "fp_addsub_<Fs>")])
+ [(set_attr "type" "fp")])
(define_insn "ceil<mode>2"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
UNSPEC_FRIP))]
- "TARGET_<MODE>_FPR && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"@
frip %0,%1
xsrdpip %x0,%x1"
- [(set_attr "type" "fp")
- (set_attr "fp_type" "fp_addsub_<Fs>")])
+ [(set_attr "type" "fp")])
(define_insn "floor<mode>2"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
UNSPEC_FRIM))]
- "TARGET_<MODE>_FPR && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"@
frim %0,%1
xsrdpim %x0,%x1"
- [(set_attr "type" "fp")
- (set_attr "fp_type" "fp_addsub_<Fs>")])
+ [(set_attr "type" "fp")])
;; No VSX equivalent to frin
(define_insn "round<mode>2"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
UNSPEC_FRIN))]
- "TARGET_<MODE>_FPR && TARGET_FPRND"
+ "TARGET_HARD_FLOAT && TARGET_FPRND"
"frin %0,%1"
- [(set_attr "type" "fp")
- (set_attr "fp_type" "fp_addsub_<Fs>")])
+ [(set_attr "type" "fp")])
(define_insn "*xsrdpi<mode>2"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
(unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Fv>")]
UNSPEC_XSRDPI))]
- "TARGET_<MODE>_FPR && TARGET_VSX"
+ "TARGET_HARD_FLOAT && TARGET_VSX"
"xsrdpi %x0,%x1"
- [(set_attr "type" "fp")
- (set_attr "fp_type" "fp_addsub_<Fs>")])
+ [(set_attr "type" "fp")])
(define_expand "lround<mode>di2"
[(set (match_dup 2)
(set (match_operand:DI 0 "gpc_reg_operand")
(unspec:DI [(match_dup 2)]
UNSPEC_FCTID))]
- "TARGET_<MODE>_FPR && TARGET_VSX"
+ "TARGET_HARD_FLOAT && TARGET_VSX"
{
operands[2] = gen_reg_rtx (<MODE>mode);
})
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(float:SF (match_operand:SI 1 "nonimmediate_operand")))]
- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
+ "TARGET_HARD_FLOAT
&& ((TARGET_FCFIDS && TARGET_LFIWAX)
- || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
+ || (TARGET_FCFID
&& (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))"
{
if (TARGET_FCFIDS && TARGET_LFIWAX)
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
- "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+ "TARGET_FCFID && TARGET_HARD_FLOAT"
"@
fcfid %0,%1
xscvsxddp %x0,%x1"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
(float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
(clobber (match_scratch:DI 2 "=d,wi"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID"
+ "TARGET_HARD_FLOAT && TARGET_FCFID"
"#"
"&& reload_completed"
[(set (match_dup 2) (match_dup 1))
(define_expand "floatdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(float:SF (match_operand:DI 1 "gpc_reg_operand")))]
- "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
+ "TARGET_FCFID && TARGET_HARD_FLOAT
&& (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
{
if (!TARGET_FCFIDS)
(define_insn "floatdisf2_fcfids"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
- && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
+ "TARGET_HARD_FLOAT && TARGET_FCFIDS"
"@
fcfids %0,%1
xscvsxdsp %x0,%x1"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
(float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
(clobber (match_scratch:DI 2 "=d,d,wi"))]
- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
- && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
+ "TARGET_HARD_FLOAT && TARGET_FCFIDS"
"#"
"&& reload_completed"
[(pc)]
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DF 2 "=d"))]
- "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_FCFIDS"
+ "TARGET_FCFID && TARGET_HARD_FLOAT && !TARGET_FCFIDS"
"#"
"&& reload_completed"
[(set (match_dup 2)
(label_ref (match_operand:DI 2 ""))
(pc)))
(set (match_dup 0) (match_dup 1))]
- "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
- && !TARGET_FCFIDS"
+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT && !TARGET_FCFIDS"
{
operands[3] = gen_reg_rtx (DImode);
operands[4] = gen_reg_rtx (CCUNSmode);
(define_expand "floatunsdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
(unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand")))]
- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
- && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
+ "TARGET_HARD_FLOAT && TARGET_FCFIDUS"
"")
(define_insn "floatunsdisf2_fcfidus"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wu")
(unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
- && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
+ "TARGET_HARD_FLOAT && TARGET_FCFIDUS"
"@
fcfidus %0,%1
xscvuxdsp %x0,%x1"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
(unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
(clobber (match_scratch:DI 2 "=d,d,wi"))]
- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
- && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
+ "TARGET_HARD_FLOAT && TARGET_FCFIDUS"
"#"
"&& reload_completed"
[(pc)]
O, wM, wS, r, wIwH,
*h, r, r, 0"))]
- "!TARGET_SINGLE_FPU &&
- (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
+ "gpc_reg_operand (operands[0], SImode)
+ || gpc_reg_operand (operands[1], SImode)"
"@
mr %0,%1
la %0,%a1
4, 4, 8, 4, 4,
4, 4, 4, 4")])
-(define_insn "*movsi_internal1_single"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
- (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
- "TARGET_SINGLE_FPU &&
- (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
- "@
- mr %0,%1
- la %0,%a1
- lwz%U1%X1 %0,%1
- stw%U0%X0 %1,%0
- li %0,%1
- lis %0,%v1
- #
- mf%1 %0
- mt%0 %1
- mt%0 %1
- nop
- stfs%U0%X0 %1,%0
- lfs%U1%X1 %0,%1"
- [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
- (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
-
;; Like movsi, but adjust a SF value to be used in a SI context, i.e.
;; (set (reg:SI ...) (subreg:SI (reg:SF ...) 0))
;;
r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
- && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
+ && TARGET_HARD_FLOAT
&& (TARGET_ALLOW_SF_SUBREG
|| valid_sf_si_move (operands[0], operands[1], SFmode))"
"@
f, r, r, *h, 0"))]
"(register_operand (operands[0], SDmode)
|| register_operand (operands[1], SDmode))
- && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
+ && TARGET_HARD_FLOAT"
"@
lwz%U1%X1 %0,%1
lfiwzx %0,%y1
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
(match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
- "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+ "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"@
(define_insn "*mov<mode>_softfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
(match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
- "! TARGET_POWERPC64
- && (TARGET_SINGLE_FLOAT || TARGET_SOFT_FLOAT)
+ "!TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"#"
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,<f64_dm>")
(match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))]
- "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+ "TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
"@
(float_extend:IBM128
(match_operand:DF 1 "nonimmediate_operand" "d,m,d")))
(use (match_operand:DF 2 "nonimmediate_operand" "m,m,d"))]
- "!TARGET_VSX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+ "!TARGET_VSX && TARGET_HARD_FLOAT
&& TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
"#"
"&& reload_completed"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d")
(float_truncate:DF (match_operand:IBM128 1 "gpc_reg_operand" "d")))]
"FLOAT128_IBM_P (<MODE>mode) && TARGET_XL_COMPAT && TARGET_HARD_FLOAT
- && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
+ && TARGET_LONG_DOUBLE_128"
"fadd %0,%1,%L1"
- [(set_attr "type" "fp")
- (set_attr "fp_type" "fp_addsub_d")])
+ [(set_attr "type" "fp")])
(define_expand "trunc<mode>sf2"
[(set (match_operand:SF 0 "gpc_reg_operand")
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float_truncate:SF (match_operand:IBM128 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DF 2 "=d"))]
- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
- && TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
+ "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
"#"
"&& reload_completed"
[(set (match_dup 2)
(unspec:DF [(match_operand:IBM128 1 "gpc_reg_operand" "d")]
UNSPEC_FIX_TRUNC_TF))
(clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && FLOAT128_IBM_P (<MODE>mode)"
+ "TARGET_HARD_FLOAT && FLOAT128_IBM_P (<MODE>mode)"
"mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
[(set_attr "type" "fp")
(set_attr "length" "20")])
(label_ref (match_operand 2 ""))
(pc)))
(set (match_dup 6) (neg:DF (match_dup 6)))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
+ "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
{
const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && TARGET_UPDATE
+ "TARGET_HARD_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
(match_operand:SF 3 "gpc_reg_operand" "f,f"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && TARGET_UPDATE
+ "TARGET_HARD_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
+ "TARGET_HARD_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
(match_operand:DF 3 "gpc_reg_operand" "d,d"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
+ "TARGET_HARD_FLOAT && TARGET_UPDATE
&& (!avoiding_indexed_address_p (SImode)
|| !gpc_reg_operand (operands[2], SImode))"
"@
(compare:CCFP (match_operand:IBM128 1 "gpc_reg_operand" "d")
(match_operand:IBM128 2 "gpc_reg_operand" "d")))]
"!TARGET_XL_COMPAT && FLOAT128_IBM_P (<MODE>mode)
- && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
+ && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
[(set_attr "type" "fpcompare")
(set_attr "length" "12")])
(clobber (match_scratch:DF 10 "=d"))
(clobber (match_scratch:GPR 11 "=b"))]
"TARGET_XL_COMPAT && FLOAT128_IBM_P (<MODE>mode)
- && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
+ && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
"#"
"&& reload_completed"
[(set (match_dup 3) (match_dup 14))
(match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>,<Fv2>")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
(match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>")))]
- "TARGET_<MODE>_FPR"
+ "TARGET_HARD_FLOAT"
"@
fmadd<Ftrad> %0,%1,%2,%3
xsmadda<Fvsx> %x0,%x1,%x2
xsmaddm<Fvsx> %x0,%x1,%x3"
- [(set_attr "type" "fp")
- (set_attr "fp_type" "fp_maddsub_<Fs>")])
+ [(set_attr "type" "fp")])
; Altivec only has fma and nfms.
(define_expand "fms<mode>4"
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
(neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>"))))]
- "TARGET_<MODE>_FPR"
+ "TARGET_HARD_FLOAT"
"@
fmsub<Ftrad> %0,%1,%2,%3
xsmsuba<Fvsx> %x0,%x1,%x2
xsmsubm<Fvsx> %x0,%x1,%x3"
- [(set_attr "type" "fp")
- (set_attr "fp_type" "fp_maddsub_<Fs>")])
+ [(set_attr "type" "fp")])
;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
(define_expand "fnma<mode>4"
(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>")
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
(match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>"))))]
- "TARGET_<MODE>_FPR"
+ "TARGET_HARD_FLOAT"
"@
fnmadd<Ftrad> %0,%1,%2,%3
xsnmadda<Fvsx> %x0,%x1,%x2
xsnmaddm<Fvsx> %x0,%x1,%x3"
- [(set_attr "type" "fp")
- (set_attr "fp_type" "fp_maddsub_<Fs>")])
+ [(set_attr "type" "fp")])
; Not an official optab name, but used from builtins.
(define_expand "nfms<mode>4"
(match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
(neg:SFDF
(match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>")))))]
- "TARGET_<MODE>_FPR"
+ "TARGET_HARD_FLOAT"
"@
fnmsub<Ftrad> %0,%1,%2,%3
xsnmsuba<Fvsx> %x0,%x1,%x2
xsnmsubm<Fvsx> %x0,%x1,%x3"
- [(set_attr "type" "fp")
- (set_attr "fp_type" "fp_maddsub_<Fs>")])
+ [(set_attr "type" "fp")])
\f
(define_expand "rs6000_get_timebase"
Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
Specify scheduling priority for dispatch slot restricted insns.
-msingle-float
-Target RejectNegative Var(rs6000_single_float) Save
-Single-precision floating point unit.
-
-mdouble-float
-Target RejectNegative Var(rs6000_double_float) Save
-Double-precision floating point unit.
-
-msimple-fpu
-Target RejectNegative Var(rs6000_simple_fpu) Save
-Floating point unit does not support divide & sqrt.
-
-mfpu=
-Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE)
--mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu).
-
-Enum
-Name(fpu_type_t) Type(enum fpu_type_t)
-
-EnumValue
-Enum(fpu_type_t) String(none) Value(FPU_NONE)
-
-EnumValue
-Enum(fpu_type_t) String(sp_lite) Value(FPU_SF_LITE)
-
-EnumValue
-Enum(fpu_type_t) String(dp_lite) Value(FPU_DF_LITE)
-
-EnumValue
-Enum(fpu_type_t) String(sp_full) Value(FPU_SF_FULL)
-
-EnumValue
-Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL)
-
-mxilinx-fpu
-Target Var(rs6000_xilinx_fpu) Save
-Specify Xilinx FPU.
-
mpointers-to-nested-functions
Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
Use r11 to hold the static link in calls to functions via pointers.
+++ /dev/null
-/* Definitions for PowerPC single-precision floating point unit
- such as Xilinx PowerPC 405/440 APU.
-
- Copyright (C) 2008-2018 Free Software Foundation, Inc.
- Contributed by Michael Eager (eager@eagercon.com)
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING3. If not see
- <http://www.gnu.org/licenses/>. */
-
-
-/* Undefine definitions from rs6000.h. */
-#undef TARGET_SINGLE_FLOAT
-#undef TARGET_DOUBLE_FLOAT
-#undef TARGET_SINGLE_FPU
-#undef TARGET_SIMPLE_FPU
-#undef UNITS_PER_FP_WORD
-
-/* FPU operations supported.
- If TARGET_SINGLE_FPU set, processor supports single fp options. */
-#define TARGET_SINGLE_FLOAT (rs6000_single_float)
-#define TARGET_DOUBLE_FLOAT (rs6000_double_float)
-#define TARGET_SINGLE_FPU 1
-#define TARGET_SIMPLE_FPU (rs6000_simple_fpu)
-
-/* FP word width depends on single/double fp support. */
-#define UNITS_PER_FP_WORD ((TARGET_SOFT_FLOAT || TARGET_DOUBLE_FLOAT) ? 8 : 4)
-
#define LINK_OS_DEFAULT_SPEC ""
-#define DRIVER_SELF_SPECS "%{mfpu=none: %<mfpu=* \
- %<msingle-float %<mdouble-float}"
-
/* Override rs6000.h definition. */
#undef CPP_SPEC
#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \
$(srcdir)/config/rs6000/power8.md \
$(srcdir)/config/rs6000/power9.md \
$(srcdir)/config/rs6000/cell.md \
- $(srcdir)/config/rs6000/xfpu.md \
$(srcdir)/config/rs6000/a2.md \
$(srcdir)/config/rs6000/predicates.md \
$(srcdir)/config/rs6000/constraints.md \
+++ /dev/null
-# Multilibs for Xilinx powerpc embedded ELF targets.
-#
-# Copyright (C) 2009-2018 Free Software Foundation, Inc.
-# Contributed by Michael Eager, eager@eagercon.com
-#
-# This file is part of GCC.
-#
-# GCC is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-#
-# GCC is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with GCC; see the file COPYING3. If not see
-# <http://www.gnu.org/licenses/>.
-
-# Switch synonyms
-MULTILIB_MATCHES = mfpu?sp_lite=msingle-float mfpu?dp_lite=mdouble-float mfpu?dp_lite=mhard-float mfpu?sp_lite=mfpu?sp_full mfpu?dp_lite=mfpu?dp_full
-
-MULTILIB_OPTIONS = mfpu=sp_lite/mfpu=dp_lite
-
-MULTILIB_DIRNAMES = single double
-
(eq_attr "cpu" "titan"))
"titan_issue,titan_fpdiv*46,titan_fpwb")
-(define_insn_reservation "titan_fp_single" 12
- (and (eq_attr "fp_type" "fp_addsub_s,fp_mul_s,fp_maddsub_s")
- (eq_attr "cpu" "titan"))
- "titan_issue,titan_fp0*2,nothing*10,titan_fpwb")
-
;; Make sure the "titan_fp" rule stays last, as it's a catch all for
;; double-precision and unclassified (e.g. fsel) FP-instructions
(define_insn_reservation "titan_fp" 10
(V4SF "vecfloat")
(DF "fp")])
-(define_mode_attr VSfptype_simple [(V2DF "fp_addsub_d")
- (V4SF "fp_addsub_s")
- (DF "fp_addsub_d")])
-
;; Appropriate type for multiply ops
(define_mode_attr VStype_mul [(V2DF "vecdouble")
(V4SF "vecfloat")
(DF "dmul")])
-(define_mode_attr VSfptype_mul [(V2DF "fp_mul_d")
- (V4SF "fp_mul_s")
- (DF "fp_mul_d")])
-
;; Appropriate type for divide ops.
(define_mode_attr VStype_div [(V2DF "vecdiv")
(V4SF "vecfdiv")
(DF "ddiv")])
-(define_mode_attr VSfptype_div [(V2DF "fp_div_d")
- (V4SF "fp_div_s")
- (DF "fp_div_d")])
-
;; Appropriate type for sqrt ops. For now, just lump the vector sqrt with
;; the scalar sqrt
(define_mode_attr VStype_sqrt [(V2DF "dsqrt")
(V4SF "ssqrt")
(DF "dsqrt")])
-(define_mode_attr VSfptype_sqrt [(V2DF "fp_sqrt_d")
- (V4SF "fp_sqrt_s")
- (DF "fp_sqrt_d")])
-
;; Iterator and modes for sp<->dp conversions
;; Because scalar SF values are represented internally as double, use the
;; V4SF type to represent this than SF.
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvadd<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_sub<mode>3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvsub<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_mul<mode>3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvmul<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_mul>")])
+ [(set_attr "type" "<VStype_simple>")])
; Emulate vector with scalar for vec_mul in V2DImode
(define_insn_and_split "vsx_mul_v2di"
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvdiv<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_div>")
- (set_attr "fp_type" "<VSfptype_div>")])
+ [(set_attr "type" "<VStype_div>")])
; Emulate vector with scalar for vec_div in V2DImode
(define_insn_and_split "vsx_div_v2di"
UNSPEC_VSX_TDIV))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>tdiv<VSs> %0,%x1,%x2"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_fre<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
UNSPEC_FRES))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvre<VSs> %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_neg<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvneg<VSs> %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_abs<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvabs<VSs> %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_nabs<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>"))))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvnabs<VSs> %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_smax<mode>3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvmax<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_smin<mode>3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvmin<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_sqrt<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvsqrt<VSs> %x0,%x1"
- [(set_attr "type" "<VStype_sqrt>")
- (set_attr "fp_type" "<VSfptype_sqrt>")])
+ [(set_attr "type" "<VStype_sqrt>")])
(define_insn "*vsx_rsqrte<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
UNSPEC_RSQRT))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvrsqrte<VSs> %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
;; *tsqrt* returning the fg flag
(define_expand "vsx_tsqrt<mode>2_fg"
UNSPEC_VSX_TSQRT))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>tsqrt<VSs> %0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
;; Fused vector multiply/add instructions. Support the classical Altivec
;; versions of fma, which allows the target to be a separate register from the
xvnmaddm<VSs> %x0,%x1,%x3
xvnmadda<VSs> %x0,%x1,%x2
xvnmaddm<VSs> %x0,%x1,%x3"
- [(set_attr "type" "<VStype_mul>")
- (set_attr "fp_type" "<VSfptype_mul>")])
+ [(set_attr "type" "<VStype_mul>")])
(define_insn "*vsx_nfmsv4sf4"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,wf,?wa,?wa,v")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcmpeq<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_gt<mode>"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcmpgt<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_ge<mode>"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcmpge<VSs> %x0,%x1,%x2"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
;; Compare vectors producing a vector result and a predicate, setting CR6 to
;; indicate a combined status
UNSPEC_COPYSIGN))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcpsgn<VSs> %x0,%x2,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
;; For the conversions, limit the register class for the integer value to be
;; the fprs because we don't want to add the altivec registers to movdi/movsi.
(float:VSX_F (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcvsx<VSc><VSs> %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_floatuns<VSi><mode>2"
[(set (match_operand:VSX_F 0 "gpc_reg_operand" "=<VSr>,?<VSa>")
(unsigned_float:VSX_F (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvcvux<VSc><VSs> %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_fix_trunc<mode><VSi>2"
[(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
(fix:<VSI> (match_operand:VSX_F 1 "gpc_reg_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>cv<VSs>sx<VSc>s %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_fixuns_trunc<mode><VSi>2"
[(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
(unsigned_fix:<VSI> (match_operand:VSX_F 1 "gpc_reg_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>cv<VSs>ux<VSc>s %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
;; Math rounding functions
(define_insn "vsx_x<VSv>r<VSs>i"
UNSPEC_VSX_ROUND_I))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>r<VSs>i %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_x<VSv>r<VSs>ic"
[(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>")
UNSPEC_VSX_ROUND_IC))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>r<VSs>ic %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_btrunc<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
(fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvr<VSs>iz %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_b2trunc<mode>2"
[(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>")
UNSPEC_FRIZ))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"x<VSv>r<VSs>iz %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_floor<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
UNSPEC_FRIM))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvr<VSs>im %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
(define_insn "vsx_ceil<mode>2"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>")
UNSPEC_FRIP))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
"xvr<VSs>ip %x0,%x1"
- [(set_attr "type" "<VStype_simple>")
- (set_attr "fp_type" "<VSfptype_simple>")])
+ [(set_attr "type" "<VStype_simple>")])
\f
;; VSX convert to/from double vector
(float:V2DF
(fix:V2DI
(match_operand:V2DF 1 "vsx_register_operand" "wd,?wa"))))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
+ "TARGET_HARD_FLOAT
&& VECTOR_UNIT_VSX_P (V2DFmode) && flag_unsafe_math_optimizations
&& !flag_trapping_math && TARGET_FRIZ"
"xvrdpiz %x0,%x1"
- [(set_attr "type" "vecdouble")
- (set_attr "fp_type" "fp_addsub_d")])
+ [(set_attr "type" "vecdouble")])
\f
;; Permute operations
+++ /dev/null
-/* Definitions for Xilinx PowerPC 405/440 APU.
-
- Copyright (C) 2008-2018 Free Software Foundation, Inc.
- Contributed by Michael Eager (eager@eagercon.com)
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING3. If not see
- <http://www.gnu.org/licenses/>. */
-
-
-/* Undefine definitions from rs6000.h. */
-#undef TARGET_XILINX_FPU
-
-#define TARGET_XILINX_FPU (rs6000_xilinx_fpu)
+++ /dev/null
-;; Scheduling description for the Xilinx PowerPC 405 APU Floating Point Unit.
-;; Copyright (C) 2008-2018 Free Software Foundation, Inc.
-;; Contributed by Michael Eager (eager@eagercon.com).
-;;
-;; This file is part of GCC.
-;;
-;; GCC is free software; you can redistribute it and/or modify
-;; it under the terms of the GNU General Public License as published by
-;; the Free Software Foundation; either version 3, or (at your option)
-;; any later version.
-;;
-;; GCC is distributed in the hope that it will be useful,
-;; but WITHOUT ANY WARRANTY; without even the implied warranty of
-;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-;; GNU General Public License for more details.
-;;
-;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING3. If not see
-;; <http://www.gnu.org/licenses/>.
-
-;;----------------------------------------------------
-;; Xilinx APU FPU Pipeline Description
-;;
-;; - attr 'type' and 'fp_type' should definitely
-;; be cleaned up at some point in the future.
-;; ddiv,sdiv,dmul,smul etc are quite confusing.
-;; Should use consistent fp* attrs. 'fp_type'
-;; should also go away, leaving us only with 'fp'
-;;
-;;----------------------------------------------------
-
-;; -------------------------------------------------------------------------
-;; Latencies
-;; Latest latency figures (all in FCB cycles). PowerPC to FPU frequency ratio
-;; assumed to be 1/2. (most common deployment)
-;; Add 2 PPC cycles for (register file access + wb) and 2 PPC cycles
-;; for issue (from PPC)
-;; SP DP
-;; Loads: 4 6
-;; Stores: 1 2 (from availability of data)
-;; Move/Abs/Neg: 1 1
-;; Add/Subtract: 5 7
-;; Multiply: 4 11
-;; Multiply-add: 10 19
-;; Convert (any): 4 6
-;; Divide/Sqrt: 27 56
-;; Compares: 1 2
-;;
-;; bypasses needed for forwarding capability of the FPU.
-;; Add this at some future time.
-;; -------------------------------------------------------------------------
-(define_automaton "Xfpu")
-(define_cpu_unit "Xfpu_issue,Xfpu_addsub,Xfpu_mul,Xfpu_div,Xfpu_sqrt" "Xfpu")
-
-
-(define_insn_reservation "fp-default" 2
- (and (and
- (eq_attr "type" "fp,fpsimple")
- (eq_attr "fp_type" "fp_default"))
- (eq_attr "cpu" "ppc405"))
- "Xfpu_issue*2")
-
-(define_insn_reservation "fp-compare" 6
- (and (eq_attr "type" "fpcompare") ;; Inconsistent naming
- (eq_attr "cpu" "ppc405"))
- "Xfpu_issue*2,Xfpu_addsub")
-
-(define_insn_reservation "fp-addsub-s" 14
- (and (and
- (eq_attr "type" "fp,fpsimple")
- (eq_attr "fp_type" "fp_addsub_s"))
- (eq_attr "cpu" "ppc405"))
- "Xfpu_issue*2,Xfpu_addsub")
-
-(define_insn_reservation "fp-addsub-d" 18
- (and (and
- (eq_attr "type" "fp,fpsimple")
- (eq_attr "fp_type" "fp_addsub_d"))
- (eq_attr "cpu" "ppc405"))
- "Xfpu_issue*2,Xfpu_addsub")
-
-(define_insn_reservation "fp-mul-s" 12
- (and (and
- (eq_attr "type" "fp")
- (eq_attr "fp_type" "fp_mul_s"))
- (eq_attr "cpu" "ppc405"))
- "Xfpu_issue*2,Xfpu_mul")
-
-(define_insn_reservation "fp-mul-d" 16 ;; Actually 28. Long latencies are killing the automaton formation. Need to figure out why.
- (and (and
- (eq_attr "type" "fp")
- (eq_attr "fp_type" "fp_mul_d"))
- (eq_attr "cpu" "ppc405"))
- "Xfpu_issue*2,Xfpu_mul")
-
-(define_insn_reservation "fp-div-s" 24 ;; Actually 34
- (and (eq_attr "type" "sdiv") ;; Inconsistent attr naming
- (eq_attr "cpu" "ppc405"))
- "Xfpu_issue*2,Xfpu_div*10") ;; Unpipelined
-
-(define_insn_reservation "fp-div-d" 34 ;; Actually 116
- (and (eq_attr "type" "ddiv")
- (eq_attr "cpu" "ppc405")) ;; Inconsistent attr naming
- "Xfpu_issue*2,Xfpu_div*10") ;; Unpipelined
-
-(define_insn_reservation "fp-maddsub-s" 24
- (and (and
- (eq_attr "type" "fp")
- (eq_attr "fp_type" "fp_maddsub_s"))
- (eq_attr "cpu" "ppc405"))
- "Xfpu_issue*2,Xfpu_mul,nothing*7,Xfpu_addsub")
-
-(define_insn_reservation "fp-maddsub-d" 34 ;; Actually 42
- (and (and
- (eq_attr "type" "dmul") ;; Inconsistent attr naming
- (eq_attr "fp_type" "fp_maddsub_d"))
- (eq_attr "cpu" "ppc405"))
- "Xfpu_issue*2,Xfpu_mul,nothing*7,Xfpu_addsub")
-
-(define_insn_reservation "fp-load" 10 ;; FIXME. Is double/single precision the same ?
- (and (eq_attr "type" "fpload")
- (eq_attr "cpu" "ppc405"))
- "Xfpu_issue*10")
-
-(define_insn_reservation "fp-store" 4
- (and (eq_attr "type" "fpstore")
- (eq_attr "cpu" "ppc405"))
- "Xfpu_issue*4")
-
-(define_insn_reservation "fp-sqrt-s" 24 ;; Actually 56
- (and (eq_attr "type" "ssqrt")
- (eq_attr "cpu" "ppc405"))
- "Xfpu_issue*2,Xfpu_sqrt*10") ;; Unpipelined
-
-
-(define_insn_reservation "fp-sqrt-d" 34 ;; Actually 116
- (and (eq_attr "type" "dsqrt")
- (eq_attr "cpu" "ppc405"))
- "Xfpu_issue*2,Xfpu_sqrt*10") ;; Unpipelined
-
+++ /dev/null
-/* Support for GCC on Xilinx embedded PowerPC systems
- Copyright (C) 2008-2018 Free Software Foundation, Inc.
- Contributed by Michael Eager, eager@eagercon.com
-
- This file is part of GCC.
-
- GCC is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published
- by the Free Software Foundation; either version 3, or (at your
- option) any later version.
-
- GCC is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GCC; see the file COPYING3. If not see
- <http://www.gnu.org/licenses/>. */
-
-/* Set defaults for Xilinx embedded target boards. */
-
-#undef CPP_SPEC
-#define CPP_SPEC "\
--mxilinx-fpu \
-%{mfpu=sp_lite: -DHAVE_XFPU_SP_LITE} \
-%{mfpu=sp_full: -DHAVE_XFPU_SP_FULL} \
-%{mfpu=dp_lite: -DHAVE_XFPU_DP_LITE} \
-%{mfpu=dp_full: -DHAVE_XFPU_DP_FULL} \
-%{mfpu=*: -DHAVE_XFPU}"
-
-#undef LIB_DEFAULT_SPEC
-#define LIB_DEFAULT_SPEC "\
-%{!nostdlib: --start-group -lxil -lc -lm --end-group \
-%{mppcperflib: %{mfpu=*: -lppcstr405 -lgcc} \
-%{!mfpu=*: -lppcstr405 -lppcfp -lgcc}} \
-%{!mppcperflib: -lgcc}}"
-
-#undef STARTFILE_DEFAULT_SPEC
-#define STARTFILE_DEFAULT_SPEC "\
-ecrti.o%s %{pg: %{!mno-clearbss: xil-pgcrt0.o%s} \
-%{mno-clearbss: xil-sim-pgcrt0.o%s}} \
-%{!pg: %{!mno-clearbss: xil-crt0.o%s} \
-%{mno-clearbss: xil-sim-crt0.o%s}} crtbegin.o%s"
-
-#undef LINK_START_DEFAULT_SPEC
-#define LINK_START_DEFAULT_SPEC "-T xilinx.ld%s"
+++ /dev/null
-; Xilinx embedded PowerPC options.
-
-; Copyright (C) 2011-2018 Free Software Foundation, Inc.
-;
-; This file is part of GCC.
-;
-; GCC is free software; you can redistribute it and/or modify it under
-; the terms of the GNU General Public License as published by the Free
-; Software Foundation; either version 3, or (at your option) any later
-; version.
-;
-; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
-; WARRANTY; without even the implied warranty of MERCHANTABILITY or
-; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-; for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with GCC; see the file COPYING3. If not see
-; <http://www.gnu.org/licenses/>.
-
-; See the GCC internals manual (options.texi) for a description of
-; this file's format.
-
-; Please try to keep this file in ASCII collating order.
-
-mno-clearbss
-Target RejectNegative
-
-mppcperflib
-Target RejectNegative
-
-; This comment is to ensure we retain the blank line above.
-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol
-malign-power -malign-natural @gol
-msoft-float -mhard-float -mmultiple -mno-multiple @gol
--msingle-float -mdouble-float -msimple-fpu @gol
-mupdate -mno-update @gol
-mavoid-indexed-addresses -mno-avoid-indexed-addresses @gol
-mfused-madd -mno-fused-madd -mbit-align -mno-bit-align @gol
@gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol
-mpopcntb -mpopcntd -mpowerpc64 @gol
--mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol
--msimple-fpu -mmulhw -mdlmzb -mmfpgpr -mvsx @gol
+-mpowerpc-gpopt -mpowerpc-gfxopt @gol
+-mmulhw -mdlmzb -mmfpgpr -mvsx @gol
-mcrypto -mhtm -mpower8-fusion -mpower8-vector @gol
-mquad-memory -mquad-memory-atomic -mfloat128 -mfloat128-hardware}
Software floating-point emulation is provided if you use the
@option{-msoft-float} option, and pass the option to GCC when linking.
-@item -msingle-float
-@itemx -mdouble-float
-@opindex msingle-float
-@opindex mdouble-float
-Generate code for single- or double-precision floating-point operations.
-@option{-mdouble-float} implies @option{-msingle-float}.
-
-@item -msimple-fpu
-@opindex msimple-fpu
-Do not generate @code{sqrt} and @code{div} instructions for hardware
-floating-point unit.
-
-@item -mfpu=@var{name}
-@opindex mfpu
-Specify type of floating-point unit. Valid values for @var{name} are
-@samp{sp_lite} (equivalent to @option{-msingle-float -msimple-fpu}),
-@samp{dp_lite} (equivalent to @option{-mdouble-float -msimple-fpu}),
-@samp{sp_full} (equivalent to @option{-msingle-float}),
-and @samp{dp_full} (equivalent to @option{-mdouble-float}).
-
-@item -mxilinx-fpu
-@opindex mxilinx-fpu
-Perform optimizations for the floating-point unit on Xilinx PPC 405/440.
-
@item -mmultiple
@itemx -mno-multiple
@opindex mmultiple
projects / gcc.git / commitdiff