split rest od ff's

diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys
index d0be205d566eb576e288d9aaeb8f45705b90bc7c..3471a0a80a9516e0de022627cb5058d2f886f459 100644 (file)
--- a/tests/efinix/adffs.ys
+++ b/tests/efinix/adffs.ys
@@ -43,9 +43,6 @@ hierarchy -top ndffnr
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
-select -assert-count 1 t:EFX_FF
-select -assert-count 1 t:EFX_GBUFCE
-
 select -assert-count 1 t:EFX_FF
 select -assert-count 1 t:EFX_GBUFCE
 select -assert-count 1 t:EFX_LUT4

diff --git a/tests/efinix/dffs.v b/tests/efinix/dffs.v
index d97840c439411c0c63b3df766a1798b5fc9caad8..3418787c9fbf25125d0e79cf11065d279df064a6 100644 (file)
--- a/tests/efinix/dffs.v
+++ b/tests/efinix/dffs.v
@@ -13,25 +13,3 @@ module dffe
                if ( en )
                        q <= d;
 endmodule
-
-module top (
-input clk,
-input en,
-input a,
-output b,b1,
-);
-
-dff u_dff (
-        .clk (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-dffe u_ndffe (
-        .clk (clk ),
-        .en (en),
-        .d (a ),
-        .q (b1 )
-    );
-
-endmodule

diff --git a/tests/efinix/dffs.ys b/tests/efinix/dffs.ys
index 557dfd3d012035c7866e0007ca3ca26a76220f3f..fe8d93123458cb18f358e42839b61103654d849c 100644 (file)
--- a/tests/efinix/dffs.ys
+++ b/tests/efinix/dffs.ys
@@ -1,12 +1,24 @@
 read_verilog dffs.v
-hierarchy -top top
+design -save read
+
 proc
-flatten
+hierarchy -top dff
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
 
+select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
+
+design -load read
+proc
+hierarchy -top dffe
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
 select -assert-count 1 t:EFX_GBUFCE
-select -assert-count 2 t:EFX_FF
 select -assert-count 1 t:EFX_LUT4
-select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D