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Added English language description for addi, addis and addpcis instruction
author
Shriya Sharma
<shriya@redsemiconductor.com>
Wed, 22 Nov 2023 14:10:23 +0000
(14:10 +0000)
committer
Shriya Sharma
<shriya@redsemiconductor.com>
Wed, 22 Nov 2023 14:10:23 +0000
(14:10 +0000)
openpower/isa/fixedarith.mdwn
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diff --git
a/openpower/isa/fixedarith.mdwn
b/openpower/isa/fixedarith.mdwn
index 4044ded9798ab2349f694de7a715cca8ec157e9a..818a28b28498e4b97002ed0b54f6622f1289e6bd 100644
(file)
--- a/
openpower/isa/fixedarith.mdwn
+++ b/
openpower/isa/fixedarith.mdwn
@@
-12,6
+12,10
@@
Pseudo-code:
RT <- (RA|0) + EXTS(SI)
+Description:
+
+ The sum (RA|0) + SI is placed into register RT.
+
Special Registers Altered:
None
@@
-26,6
+30,11
@@
Pseudo-code:
RT <- (RA|0) + EXTS(SI || [0]*16)
+Description:
+
+ The sum (RA|0) + (SI || 0x0000) is placed into register
+ RT.
+
Special Registers Altered:
None
@@
-41,6
+50,11
@@
Pseudo-code:
D <- d0||d1||d2
RT <- NIA + EXTS(D || [0]*16)
+Description:
+
+ The sum of NIA + (D || 0x0000) is placed into register
+ RT.
+
Special Registers Altered:
None