soc: move SoCController from soc_core to soc

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index f513777de2e5fce44011dcdbc4f2f2445782f74e..7d43efaaea782955590d5453d110c00a6e1ad8c8 100755 (executable)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -9,6 +9,7 @@ import datetime
 
 from migen import *
 
+from litex.soc.interconnect.csr import *
 from litex.soc.interconnect import wishbone
 
 # TODO:
@@ -424,6 +425,34 @@ class SoCIRQHandler(SoCLocHandler):
         r = r[:-1]
         return r
 
+# SoCController ------------------------------------------------------------------------------------
+
+class SoCController(Module, AutoCSR):
+    def __init__(self):
+        self._reset      = CSRStorage(1, description="""
+            Write a ``1`` to this register to reset the SoC.""")
+        self._scratch    = CSRStorage(32, reset=0x12345678, description="""
+            Use this register as a scratch space to verify that software read/write accesses
+            to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578
+            can be used to verify endianness.""")
+        self._bus_errors = CSRStatus(32, description="""
+            Total number of Wishbone bus errors (timeouts) since last reset.""")
+
+        # # #
+
+        # Reset
+        self.reset = Signal()
+        self.comb += self.reset.eq(self._reset.re)
+
+        # Bus errors
+        self.bus_error = Signal()
+        bus_errors     = Signal(32)
+        self.sync += \
+            If(bus_errors != (2**len(bus_errors)-1),
+                If(self.bus_error, bus_errors.eq(bus_errors + 1))
+            )
+        self.comb += self._bus_errors.status.eq(bus_errors)
+
 # SoC ----------------------------------------------------------------------------------------------
 
 class SoC(Module):

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 1f71098fe3487b5c52d079d5c6c51e94f307aa12..55ec3b87dc50c9187623b223290c69d1154e4633 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -22,10 +22,9 @@ from litex.build.tools import deprecated_warning
 
 from litex.soc.cores import identifier, timer, uart
 from litex.soc.cores import cpu
-from litex.soc.interconnect.csr import *
 from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr
 from litex.soc.integration.common import *
-from litex.soc.integration.soc import SoCRegion, SoC
+from litex.soc.integration.soc import SoCRegion, SoC, SoCController
 
 __all__ = [
     "mem_decoder",
@@ -38,36 +37,6 @@ __all__ = [
     "soc_mini_argdict",
 ]
 
-# SoCController ------------------------------------------------------------------------------------
-
-class SoCController(Module, AutoCSR):
-    def __init__(self):
-        self._reset      = CSRStorage(1, description="""
-            Write a ``1`` to this register to reset the SoC.""")
-        self._scratch    = CSRStorage(32, reset=0x12345678, description="""
-            Use this register as a scratch space to verify that software read/write accesses
-            to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578
-            can be used to verify endianness.""")
-        self._bus_errors = CSRStatus(32, description="""
-            Total number of Wishbone bus errors (timeouts) since last reset.""")
-
-        # # #
-
-        # reset
-        self.reset = Signal()
-        self.comb += self.reset.eq(self._reset.re)
-
-        # bus errors
-        self.bus_error = Signal()
-        bus_errors     = Signal(32)
-        self.sync += \
-            If(bus_errors != (2**len(bus_errors)-1),
-                If(self.bus_error,
-                    bus_errors.eq(bus_errors + 1)
-                )
-            )
-        self.comb += self._bus_errors.status.eq(bus_errors)
-
 # SoCCore ------------------------------------------------------------------------------------------
 
 class SoCCore(SoC):