It's flushed by calling r600_context_bo_reloc.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
util_range_add(&rdst->valid_buffer_range, dst_offset,
dst_offset + size);
- /* make sure that the dma ring is only one active */
- rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
dst_offset += r600_resource_va(&rctx->screen->b.b, dst);
src_offset += r600_resource_va(&rctx->screen->b.b, src);
unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
uint64_t base, addr;
- /* make sure that the dma ring is only one active */
- rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
-
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
/* downcast linear aligned to linear to simplify test */
util_range_add(&rdst->valid_buffer_range, dst_offset,
dst_offset + size);
- /* make sure that the dma ring is only one active */
- rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
-
size >>= 2;
shift = 2;
ncopy = (size / 0xffff) + !!(size % 0xffff);
unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
uint64_t base, addr;
- /* make sure that the dma ring is only one active */
- rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
-
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
/* downcast linear aligned to linear to simplify test */