(no commit message)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index b5f78a1f0f0c7192c7aa70209bd6ac85d02625f1..0b0030a574eb2e4e05082bae2a3d8b261f820a4e 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -84,7 +84,6 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 |sz |SNZ| 0 RG  |   0 | dz  /   | simple mode                      |
 |sz |SNZ| 0 RG  |   1 | 0   /   | scalar reduce mode (mapreduce), SUBVL=1 |
 |zz |SNZ| 0 RG  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
-|zz |SNZ| 0 RG  |   1 | SVM 1   | Pack/Unpack mode, SUBVL>1   |
 |zz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |
 |sz |SNZ| 1 VLI | inv |  dz /   | Ffirst 5-bit mode       |
 
@@ -210,23 +209,6 @@ Implementations are free and clear to optimise these reductions in any
 way they see fit, as long as the end-result is compatible with Strict Program
 Order being observed, and Interrupt latency is not adversely impacted.
 
-# LD/ST Pack/Unpack Mode
-
-As described in [[sv/normal]], 
-Structured Pack/Unpack is similar to VSX `vpack` and `vunpack` except
-generalised not only to a Schedule to be applied to any operation but
-also extended to vec2/3/4.
-
-Like in [[sv/normal]] and [sv/ldst]] operations, 
-setting this mode changes the meaning of bits 4-5 in `RM` from being
-`ELWIDTH` to a pair of Pack/Unpack bits. 
-*Unlike* in other operation categories however,
-the `SRC_ELWIDTH` bits (6-7) are in use for `SNZ`.
-Therefore **it is not possible to use elwidth overrides and Pack/Unpack**
-at the same time.  With elwidths being meaningless for CR Fields this was
-considered an acceptable compromise: the operations particularly affected
-are extremely weird CR ops.
-
 # Unusual and quirky CR operations
 
 ## cmp and other compare ops