hdl.ir: lower domains before resolving hierarchy conflicts.

Otherwise, two subfragments with the same local clock domain would
not be able to drive its clock or reset signals. This can be easily
hit if using two ResetSynchronizers in one module.

Fixes #265.

diff --git a/nmigen/hdl/ir.py b/nmigen/hdl/ir.py
index c213943887ccf498254f83d6b2affb6e5b542c3a..1df1b87b9a63c2b33cb53f181560e41b730e6109 100644 (file)
--- a/nmigen/hdl/ir.py
+++ b/nmigen/hdl/ir.py
@@ -540,8 +540,8 @@ class Fragment:
 
         fragment = SampleLowerer()(self)
         new_domains = fragment._propagate_domains(missing_domain)
-        fragment._resolve_hierarchy_conflicts()
         fragment = DomainLowerer()(fragment)
+        fragment._resolve_hierarchy_conflicts()
         if ports is None:
             fragment._propagate_ports(ports=(), all_undef_as_ports=True)
         else:

diff --git a/nmigen/test/test_hdl_ir.py b/nmigen/test/test_hdl_ir.py
index 5c86b646f42bde3631aa9af6f01c7b55637ae312..74a909624600da3f69442b7542456de0cec17742 100644 (file)
--- a/nmigen/test/test_hdl_ir.py
+++ b/nmigen/test/test_hdl_ir.py
@@ -642,6 +642,20 @@ class FragmentHierarchyConflictTestCase(FHDLTestCase):
         self.f1._resolve_hierarchy_conflicts(mode="silent")
         self.assertEqual(self.f1.subfragments, [])
 
+    def test_no_conflict_local_domains(self):
+        f1 = Fragment()
+        cd1 = ClockDomain("d", local=True)
+        f1.add_domains(cd1)
+        f1.add_driver(ClockSignal("d"))
+        f2 = Fragment()
+        cd2 = ClockDomain("d", local=True)
+        f2.add_domains(cd2)
+        f2.add_driver(ClockSignal("d"))
+        f3 = Fragment()
+        f3.add_subfragment(f1)
+        f3.add_subfragment(f2)
+        f3.prepare()
+
 
 class InstanceTestCase(FHDLTestCase):
     def test_construct(self):