(no commit message)

diff --git a/openpower/isans_letter.mdwn b/openpower/isans_letter.mdwn
index 4cb9dd1e614271ae93fd454d2f89782f0f70a3fc..ec83077329a18428864d186efc99e0c7403434d4 100644 (file)
--- a/openpower/isans_letter.mdwn
+++ b/openpower/isans_letter.mdwn
@@ -2,8 +2,17 @@
 
 # Letter regarding ISAMUX / NS
 
+## Summary of the Libre-SOC project
+
+* We propose a standard way of extending the PowerPC Instruction Set Architecture (PPC ISA) enabling many different individuals within a well supported family.
+* This will facilitate the use of PPC in novel or niche applications without breaking the PPC ISA into incompatible islands - this is about more than just our project.
+* Libre-SOC's project is to extend the PPC to integrate GPU and VPU functionality into the PPC ISA. By not needing separate chips this will enable lower cost systems to be built so giving PPC a competitive market advantage.
+* Libre-SOC's extensions will be easily adopted as the standard Linux distributions will run on our ISA without needing any extra work.
+
+## One CPU multiple ISAs
+
 This is a quick overview of the way that we would like to add changes
-that we are proposing to the PowerPC instruction set.  It is based on
+that we are proposing to the PowerPC instruction set (ISA).  It is based on
 a Open Standardisation of the way that existing "mode switches",
 already found in the POWER instruction set, are added:
 
@@ -12,6 +21,8 @@ already found in the POWER instruction set, are added:
 * MSR's "SF" bit, setting either 32-bit or 64-bit mode
 * PCR's "compatibility" bits 60-62, V2.05 V2.06 V2.07 mode
 
+These effectively create multiple, incompatible ISAs within one CPU. They are selectable for the needs of the individual program being run.
+
 All of these are set by one instruction, that, once set, radically
 changes the entire behaviour and characteristics of subsequent instructions.
 
@@ -34,6 +45,8 @@ include ATAN2, LOG, NORMALISE, YUV2RGB, Khronos Compliance FP mode
 these may turn out to be useful in a wider context: they however need
 to be fully isolated behind "mode-setting".
 
+Some mode-setting instructions are privileged, ie can only be set by the kernel (eg 32 or 64 bit mode). The escape sequences that we propose will be usable without the need for an expensive system call over head.
+
 # Summary of Libre-SOC Commercial Project
 
 The Libre-SOC Commercial Product is a hybrid GPU-GPU-VPU intended for
@@ -83,3 +96,12 @@ option is to extend the POWER ISA in an atomically-managed (IANA-style)
 formal fashion, whilst (critically and absolutely essentially) always
 providing a PCR compatibility mode that is fully POWER compliant.
 
+## Why has Libre-SOC chosen PowerPC ?
+
+Our choice was between RISC-V and PowerPC.
+
+The PowerPC architecture is more complete and mature than RISC-V which we initially looked at. It also has a deeper adoption by Linux distributions
+
+Following IBM's release of the Power Architecture instruction set to the Linux Foundation in August 2019 the barrier to using it is no more than that of using RISC-V. We are encouraged that the OpenPOWER Foundation is supportive of what we are doing and helping, eg by putting us in touch with people who can help us.
+
+