Added spice testbench to techlibs/cmos

diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index a2be5d0b5869345497980e27f7f19b6ea068e8d1..327e1b31abc0da371e24268a01c8c9c83589d989 100644 (file)
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -165,9 +165,6 @@ struct SpiceBackend : public Backend {
                fprintf(f, "* SPICE netlist, generated by Yosys *\n");
                fprintf(f, "*************************************\n");
                fprintf(f, "\n");
-               fprintf(f, ".GLOBAL %s\n", neg.c_str());
-               fprintf(f, ".GLOBAL %s\n", pos.c_str());
-               fprintf(f, "\n");
 
                for (auto module_it : design->modules)
                {

diff --git a/techlibs/cmos/cmos_cells.sp b/techlibs/cmos/cmos_cells.sp
new file mode 100644 (file)
index 0000000..cb94caa
--- /dev/null
+++ b/techlibs/cmos/cmos_cells.sp
@@ -0,0 +1,34 @@
+
+.SUBCKT NOT A Y
+M1 Y A Vdd Vdd cmosp L=1u W=10u
+M2 Y A Vss Vss cmosn L=1u W=10u
+.ENDS NOT
+
+.SUBCKT NAND A B Y
+M1 Y A Vdd Vdd cmosp L=1u W=10u
+M2 Y B Vdd Vdd cmosp L=1u W=10u
+M3 Y A M34 Vss cmosn L=1u W=10u
+M4 M34 B Vss Vss cmosn L=1u W=10u
+.ENDS NAND
+
+.SUBCKT NOR A B Y
+M1 Y A M12 Vdd cmosp L=1u W=10u
+M2 M12 B Vdd Vdd cmosp L=1u W=10u
+M3 Y A Vss Vss cmosn L=1u W=10u
+M4 Y B Vss Vss cmosn L=1u W=10u
+.ENDS NOR
+
+.SUBCKT DLATCH E D Q
+X1 D E S NAND
+X2 nD E R NAND
+X3 S nQ Q NAND
+X4 Q R nQ NAND
+X5 D nD NOT
+.ENDS DLATCH
+
+.SUBCKT DFF C D Q
+X1 nC D t DLATCH
+X2 C t Q DLATCH
+X3 C nC NOT
+.ENDS DFF
+

diff --git a/techlibs/cmos/counter.v b/techlibs/cmos/counter.v
index 72208bd80d14fe87cb2bc042c8f45911c05a848b..68b5c05b6fd364a02d3e88b4784910607c71505b 100644 (file)
--- a/techlibs/cmos/counter.v
+++ b/techlibs/cmos/counter.v
@@ -1,12 +1,12 @@
 module counter (clk, rst, en, count);
 
    input clk, rst, en;
-   output reg [3:0] count;
+   output reg [2:0] count;
    
    always @(posedge clk)
       if (rst)
-         count <= 4'd0;
+         count <= 3'd0;
       else if (en)
-         count <= count + 4'd1;
+         count <= count + 3'd1;
 
 endmodule

diff --git a/techlibs/cmos/testbench.sh b/techlibs/cmos/testbench.sh
new file mode 100644 (file)
index 0000000..061704b
--- /dev/null
+++ b/techlibs/cmos/testbench.sh
@@ -0,0 +1,7 @@
+#!/bin/bash
+
+set -ex
+
+../../yosys counter.ys
+ngspice testbench.sp
+

diff --git a/techlibs/cmos/testbench.sp b/techlibs/cmos/testbench.sp
new file mode 100644 (file)
index 0000000..95d2f67
--- /dev/null
+++ b/techlibs/cmos/testbench.sp
@@ -0,0 +1,29 @@
+
+* supply voltages
+.global Vss Vdd
+Vss Vss 0 DC 0
+Vdd Vdd 0 DC 3
+
+* simple transistor model
+.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
+
+* load design and library
+.include synth.sp
+.include cmos_cells.sp
+
+* input signals
+Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2)
+Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40)
+Ven  en  0 PULSE(0 3 0.5 0.1 0.1 5.9 8)
+
+Xuut clk rst en out0 out1 out2 COUNTER
+
+.tran 0.01 50
+
+.control
+run
+plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30
+.endc
+
+.end