RISC-V: Disable the CSR checking by default.

Add new .option `csr-check/no-csr-check` and GAS option `-mcsr-check
/-mno-csr-check` to enbale/disable the CSR checking.  Disable the CSR
checking by default.

	gas/
	* config/tc-riscv.c: Add new .option and GAS options to enbale/disable
	the CSR checking.  We disable the CSR checking by default.
	(reg_lookup_internal): Check the `riscv_opts.csr_check`
	before we doing the CSR checking.

	* doc/c-riscv.texi: Add description for the new .option and assembler
	options.

	* testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable
	the CSR checking.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 904d45a0d75bed40dbd57e9858478f9b50e28015..643f8c7e45b7aad714a522a33a17f60243d7560b 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,19 @@
 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 
+       * config/tc-riscv.c (struct riscv_set_options): New field csr_check.
+       (riscv_opts): Initialize it.
+       (reg_lookup_internal): Check the `riscv_opts.csr_check`
+       before doing the CSR checking.
+       (enum options): Add OPTION_CSR_CHECK and OPTION_NO_CSR_CHECK.
+       (md_longopts): Add mcsr-check and mno-csr-check.
+       (md_parse_option): Handle new enum option values.
+       (s_riscv_option): Handle new long options.
+       * doc/c-riscv.texi: Add description for the new .option and assembler
+       options.
+       * testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable
+       the CSR checking.
+       * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
+
        * config/tc-riscv.c (csr_extra_hash): New.
        (enum riscv_csr_class): New enum.  Used to decide
        whether or not this CSR is legal in the current ISA string.

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 2f95d41ce94b6a8f6c781b680d0dfc8197948815..5972f02656d61698dd1f7c2ba53bf4ef4f98e6f9 100644 (file)
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -83,6 +83,7 @@ struct riscv_set_options
   int rve; /* Generate RVE code.  */
   int relax; /* Emit relocs the linker is allowed to relax.  */
   int arch_attr; /* Emit arch attribute.  */
+  int csr_check; /* Enable the CSR checking.  */
 };
 
 static struct riscv_set_options riscv_opts =
@@ -92,6 +93,7 @@ static struct riscv_set_options riscv_opts =
   0,   /* rve */
   1,   /* relax */
   DEFAULT_RISCV_ATTR, /* arch_attr */
+  0.   /* csr_check */
 };
 
 static void
@@ -572,7 +574,9 @@ reg_lookup_internal (const char *s, enum reg_class class)
   if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
     return -1;
 
-  if (class == RCLASS_CSR && !reg_csr_lookup_internal (s))
+  if (class == RCLASS_CSR
+      && riscv_opts.csr_check
+      && !reg_csr_lookup_internal (s))
     return -1;
 
   return DECODE_REG_NUM (r);
@@ -2272,6 +2276,8 @@ enum options
   OPTION_NO_RELAX,
   OPTION_ARCH_ATTR,
   OPTION_NO_ARCH_ATTR,
+  OPTION_CSR_CHECK,
+  OPTION_NO_CSR_CHECK,
   OPTION_END_OF_ENUM
 };
 
@@ -2286,6 +2292,8 @@ struct option md_longopts[] =
   {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
   {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
   {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
+  {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
+  {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
 
   {NULL, no_argument, NULL, 0}
 };
@@ -2364,6 +2372,14 @@ md_parse_option (int c, const char *arg)
       riscv_opts.arch_attr = FALSE;
       break;
 
+    case OPTION_CSR_CHECK:
+      riscv_opts.csr_check = TRUE;
+      break;
+
+    case OPTION_NO_CSR_CHECK:
+      riscv_opts.csr_check = FALSE;
+      break;
+
     default:
       return 0;
     }
@@ -2756,6 +2772,10 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
     riscv_opts.relax = TRUE;
   else if (strcmp (name, "norelax") == 0)
     riscv_opts.relax = FALSE;
+  else if (strcmp (name, "csr-check") == 0)
+    riscv_opts.csr_check = TRUE;
+  else if (strcmp (name, "no-csr-check") == 0)
+    riscv_opts.csr_check = FALSE;
   else if (strcmp (name, "push") == 0)
     {
       struct riscv_option_stack *s;

diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 739670fafe32e0daff7b6dc49ad4120f69f30bc5..599b5cf8afeb8b0d027b3ce4632e8d400eb9f6f6 100644 (file)
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -73,6 +73,15 @@ specification.
 Don't generate the default riscv elf attribute section if the .attribute
 directives are not set.
 
+@cindex @samp{-mcsr-check} option, RISC-V
+@item -mcsr-check
+Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
+The ISA-dependent CSR are only valid when the specific ISA is set.  The
+read-only CSR can not be written by the CSR instructions.
+
+@cindex @samp{-mno-csr-check} option, RISC-V
+@item -mno-csr-check
+Don't do CSR cheching.
 @end table
 @c man end
 
@@ -174,6 +183,10 @@ opportunistically relax some code sequences, but sometimes this behavior is not
 desirable.
 @end table
 
+@item csr-check
+@itemx no-csr-check
+Enables or disables the CSR checking.
+
 @cindex INSN directives
 @item .insn @var{value}
 @itemx .insn @var{value}

diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
index 78ab75878d8a0bb8582f7bf85985bf52795967aa..da5356636934b73b397e728faa45e3188506107c 100644 (file)
--- a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
@@ -1,3 +1,3 @@
-#as: -march=rv32i
+#as: -march=rv32i -mcsr-check
 #source: priv-reg.s
 #warning_output: priv-reg-fail-fext.l

diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
index 5dc840a80ee08c04e195c1e7edf0a63f73eb88d5..d71b2615c5f1463f347f9a92d070f664f9db4890 100644 (file)
--- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
@@ -1,3 +1,3 @@
-#as: -march=rv64if
+#as: -march=rv64if -mcsr-check
 #source: priv-reg.s
 #warning_output: priv-reg-fail-rv32-only.l