Reorganized the MiscRegFile

--HG--
extra : convert_revision : 088112c9b8a4ea09c8015da5a0b65ed2fc9398d2

diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index efaa22f67544d4803d4622d16a6832a94b7e64f3..ada3c18e7404b306ced67f59ef59c64d38bcf963 100644 (file)
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -221,8 +221,6 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg,
           }
           return tc->getCpuPtr()->curCycle() - tickFields.counter |
               tickFields.npt << 63;
-        case MISCREG_PC:
-          return tc->readPC();
         case MISCREG_FPRS:
           fault = new UnimpFault("FPU not implemented\n");
           return 0;
@@ -280,112 +278,115 @@ Fault MiscRegFile::setReg(int miscReg, const MiscReg &val)
     switch (miscReg) {
         case MISCREG_Y:
           y = val;
-          return NoFault;
+          break;
         case MISCREG_CCR:
           ccr = val;
-          return NoFault;
+          break;
         case MISCREG_ASI:
           asi = val;
-          return NoFault;
+          break;
         case MISCREG_FPRS:
           fprs = val;
-          return NoFault;
+          break;
         case MISCREG_TICK:
-           tick = val;
-          return NoFault;
+          tick = val;
+          break;
         case MISCREG_PCR:
         case MISCREG_PIC:
           panic("ASR number %d not implemented\n", miscReg - AsrStart);
         case MISCREG_GSR:
           gsr = val;
+          break;
         case MISCREG_SOFTINT:
-           softint = val;
-          return NoFault;
+          softint = val;
+          break;
         case MISCREG_TICK_CMPR:
-           tick_cmpr = val;
-          return NoFault;
+          tick_cmpr = val;
+          break;
         case MISCREG_STICK:
-           stick = val;
-          return NoFault;
+          stick = val;
+          break;
         case MISCREG_STICK_CMPR:
-           stick_cmpr = val;
-          return NoFault;
+          stick_cmpr = val;
+          break;
 
         /** Privilged Registers */
         case MISCREG_TPC:
           tpc[tl-1] = val;
-          return NoFault;
+          break;
         case MISCREG_TNPC:
           tnpc[tl-1] = val;
-          return NoFault;
+          break;
         case MISCREG_TSTATE:
           tstate[tl-1] = val;
-          return NoFault;
+          break;
         case MISCREG_TT:
           tt[tl-1] = val;
-          return NoFault;
+          break;
         case MISCREG_PRIVTICK:
           panic("Priviliged access to tick regesiters not implemented\n");
         case MISCREG_TBA:
-          tba = val;
-          return NoFault;
+          // clear lower 7 bits on writes.
+          tba = val & ULL(~0x7FFF);
+          break;
         case MISCREG_PSTATE:
           pstate = val;
-          return NoFault;
+          break;
         case MISCREG_TL:
           tl = val;
-          return NoFault;
+          break;
         case MISCREG_PIL:
           pil = val;
-          return NoFault;
+          break;
         case MISCREG_CWP:
           cwp = val;
-          return NoFault;
+          break;
         case MISCREG_CANSAVE:
           cansave = val;
-          return NoFault;
+          break;
         case MISCREG_CANRESTORE:
           canrestore = val;
-          return NoFault;
+          break;
         case MISCREG_CLEANWIN:
           cleanwin = val;
-          return NoFault;
+          break;
         case MISCREG_OTHERWIN:
           otherwin = val;
-          return NoFault;
+          break;
         case MISCREG_WSTATE:
           wstate = val;
-          return NoFault;
+          break;
         case MISCREG_GL:
           gl = val;
-          return NoFault;
+          break;
 
         /** Hyper privileged registers */
         case MISCREG_HPSTATE:
           hpstate = val;
-          return NoFault;
+          break;
         case MISCREG_HTSTATE:
           htstate[tl-1] = val;
-          return NoFault;
+          break;
         case MISCREG_HINTP:
           panic("HINTP not implemented\n");
         case MISCREG_HTBA:
           htba = val;
-          return NoFault;
+          break;
         case MISCREG_STRAND_STS_REG:
           strandStatusReg = val;
-          return NoFault;
+          break;
         case MISCREG_HSTICK_CMPR:
           hstick_cmpr = val;
-          return NoFault;
+          break;
 
         /** Floating Point Status Register */
         case MISCREG_FSR:
           fsr = val;
-          return NoFault;
+          break;
         default:
           panic("Miscellaneous register %d not implemented\n", miscReg);
     }
+    return NoFault;
 }
 
 Fault MiscRegFile::setRegWithEffect(int miscReg,
@@ -393,91 +394,25 @@ Fault MiscRegFile::setRegWithEffect(int miscReg,
 {
     const uint64_t Bit64 = (1ULL << 63);
     switch (miscReg) {
-        case MISCREG_Y:
-        case MISCREG_CCR:
-        case MISCREG_ASI:
-          setReg(miscReg, val);
-          return NoFault;
-        case MISCREG_PRIVTICK:
         case MISCREG_TICK:
-          if (isNonPriv())
-              return new PrivilegedOpcode;
-          if (isPriv())
-              return new PrivilegedAction;
           tickFields.counter = tc->getCpuPtr()->curCycle() - val  & ~Bit64;
           tickFields.npt = val & Bit64 ? 1 : 0;
-           return NoFault;
-        case MISCREG_PC:
-           return new IllegalInstruction;
+          break;
         case MISCREG_FPRS:
-           return new UnimpFault("FPU not implemented\n");
+          //Configure the fpu based on the fprs
+          break;
         case MISCREG_PCR:
-           return new UnimpFault("Performance Instrumentation not impl\n");
-        case MISCREG_PIC:
-           return new UnimpFault("Performance Instrumentation not impl\n");
-        case MISCREG_GSR:
-           return setReg(miscReg, val);
-
-        /** Privilged Registers */
-        case MISCREG_TPC:
-        case MISCREG_TNPC:
-        case MISCREG_TSTATE:
-        case MISCREG_TT:
-          if (tl == 0)
-              return new IllegalInstruction;
-          setReg(miscReg, val);
-          return NoFault;
-
-        case MISCREG_TBA:
-          // clear lower 7 bits on writes.
-          setReg(miscReg, val & ULL(~0x7FFF));
-          return NoFault;
-
-        case MISCREG_PSTATE:
-          setReg(miscReg, val);
-          return NoFault;
-
-        case MISCREG_TL:
-          if (isHyperPriv() && val > MaxTL)
-              setReg(miscReg, MaxTL);
-          else if (isPriv() && !isHyperPriv() && val > MaxPTL)
-              setReg(miscReg, MaxPTL);
-          else
-              setReg(miscReg, val);
-          return NoFault;
-
+          //Set up performance counting based on pcr value
+          break;
         case MISCREG_CWP:
           tc->changeRegFileContext(CONTEXT_CWP, val);
-        case MISCREG_CANSAVE:
-        case MISCREG_CANRESTORE:
-        case MISCREG_CLEANWIN:
-        case MISCREG_OTHERWIN:
-        case MISCREG_WSTATE:
-          setReg(miscReg, val);
-          return NoFault;
-
+          break;
         case MISCREG_GL:
-          int newval;
-          if (isHyperPriv() && val > MaxGL)
-              newval = MaxGL;
-          else if (isPriv() && !isHyperPriv() && val > MaxPGL)
-              newval =  MaxPGL;
-          else
-              newval = val;
-          tc->changeRegFileContext(CONTEXT_GLOBALS, newval);
-          setReg(miscReg, newval);
-          return NoFault;
-
-        /** Floating Point Status Register */
-        case MISCREG_FSR:
-          setReg(miscReg, val);
-        default:
-#if FULL_SYSTEM
-              setFSRegWithEffect(miscReg, val, tc);
-#else
-              return new IllegalInstruction;
-#endif
+          tc->changeRegFileContext(CONTEXT_GLOBALS, val);
+          break;
     }
+    setReg(miscReg, val);
+    return NoFault;
 }
 
 void MiscRegFile::serialize(std::ostream & os)

diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index be143311f89fc5ca7f802e42e96cb8b24d65606a..0d81dae1ea7490cd60bb1775750f0177e9020584 100644 (file)
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -56,7 +56,6 @@ namespace SparcISA
         MISCREG_CCR = AsrStart + 2,
         MISCREG_ASI = AsrStart + 3,
         MISCREG_TICK = AsrStart + 4,
-        MISCREG_PC = AsrStart + 5,
         MISCREG_FPRS = AsrStart + 6,
         MISCREG_PCR = AsrStart + 16,
         MISCREG_PIC = AsrStart + 17,